1. 15 Aug, 2018 5 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu',... · d16adaf0
      Stephen Boyd authored
      Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next
      
      * clk-mvebu-spdx:
        clk: mvebu: armada-37xx-periph: switch to SPDX license identifier
      
      * clk-meson:
        clk: meson: add gen_clk
        clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
        clk: meson-axg: add clocks required by pcie driver
        clk: meson: remove unused clk-audio-divider driver
        clk: meson: stop rate propagation for audio clocks
        clk: meson: axg: add the audio clock controller driver
        clk: meson: add axg audio sclk divider driver
        clk: meson: add triple phase clock driver
        clk: meson: add clk-phase clock driver
        clk: meson: clean-up meson clock configuration
        clk: meson: remove obsolete register access
        clk: meson: expose GEN_CLK clkid
        clk: meson-axg: add pcie and mipi clock bindings
        dt-bindings: clock: add meson axg audio clock controller bindings
        clk: meson: audio-divider is one based
        clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
      
      * clk-imx7d-mu:
        :  - i.MX7D mailbox clk support
        clk: imx7d: add IMX7D_MU_ROOT_CLK
      
      * clk-imx-init-array-cleanup:
        :  - i.MX clk init arrays removed in place of CLK_IS_CRITICAL
        clk: imx6sx: remove clks_init_on array
        clk: imx6sl: remove clks_init_on array
        clk: imx6q: remove clks_init_on array
      
      * clk-rockchip:
        clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
        clk: rockchip: fix clk_i2sout parent selection bits on rk3399
        clk: rockchip: add clock controller for px30
        clk: rockchip: add support for half divider
        dt-bindings: add bindings for px30 clock controller
        clk: rockchip: add dt-binding header for px30
      d16adaf0
    • Stephen Boyd's avatar
      Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124',... · 13905463
      Stephen Boyd authored
      Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next
      
      * clk-imx-critical:
        :  - Convert to CLK_IS_CRITICAL for i.MX51/53 driver
        clk: imx51-imx53: Include sizes.h to silence compile errors
        clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL
      
      * clk-tegra-bpmp:
        :  - Fix Tegra BPMP driver oops when some xlating a NULL clk
        clk: tegra: bpmp: Don't crash when a clock fails to register
      
      * clk-tegra-124:
        :  - Proper default configuration for vic03 and vde clks on Tegra124
        clk: tegra: Make vde a child of pll_c3
        clk: tegra: Make vic03 a child of pll_c3
      
      * clk-tegra-critical:
        :  - Mark Tegra memory controller clks as critical
        clk: tegra: Mark Memory Controller clock as critical
      
      * clk-tegra-emc-oob:
        :  - Fix array bounds clamp in Tegra's emc determine_rate() op
        clk: tegra: emc: Avoid out-of-bounds bug
      13905463
    • Stephen Boyd's avatar
      Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll',... · ea4f7872
      Stephen Boyd authored
      Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next
      
      * clk-ingenic-fixes:
        :  - Ingenic i2s bit update and allow UDC clk to gate
        clk: ingenic: Add missing flag for UDC clock
        clk: ingenic: Fix incorrect data for the i2s clock
      
      * clk-max9485:
        :  - Maxim 9485 Programmable Clock Generator
        clk: Add driver for MAX9485
        dts: clk: add devicetree bindings for MAX9485
      
      * clk-pxa-32k-pll:
        :  - Expose 32 kHz PLL on PXA SoCs
        clk: pxa: export 32kHz PLL
      
      * clk-aspeed:
        :  - Fix name of aspeed SDC clk define to have only one 'CLK'
        clk: aspeed: Fix SDCLK name
      
      * clk-imx6sll-gpio:
        :  - imx6sll GPIO clk gate support
        clk: imx6sll: add GPIO LPCGs
      ea4f7872
    • Stephen Boyd's avatar
      Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals',... · b183c688
      Stephen Boyd authored
      Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next
      
      * clk-imx6-video-parent:
        :  - Fix i.MX6QDL video clk parent
        clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL
      
      * clk-qcom-sdm845-criticals:
        :  - critical clk markings for qcom SDM845
        clk: qcom: Enable clocks which needs to be always on for SDM845
      
      * clk-renesas:
        clk: renesas: Renesas R9A06G032 clock driver
        dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
        dt-bindings: clock: Add the r9a06g032-sysctrl.h file
        clk: renesas: r8a7795: Add CCREE clock
        clk: renesas: r8a7795: Add CR clock
      
      * clk-stratix10-fixes:
        :  - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
        clk: socfpga: stratix10: fix the sdmmc_free_clk mux
        clk: socfpga: stratix10: fix the parents of mpu_free_clk
      
      * clk-atmel-i2s:
        :  - Atmel at91 I2S audio clk support
        clk: at91: add I2S clock mux driver
        dt-bindings: clk: at91: add an I2S mux clock
      b183c688
    • Stephen Boyd's avatar
      Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate',... · 5ef7748b
      Stephen Boyd authored
      Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', 'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next
      
      * clk-qcom-set-rate-gate:
        clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks
      
      * clk-core-set-rate-gate:
        clk: fix CLK_SET_RATE_GATE with clock rate protection
      
      * clk-core-duty-cycle:
        clk: add duty cycle support
      
      * clk-si-prepare:
        :  - SI544/SI514 clk on/off support
        clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations
      
      * clk-imx-gpio-gates:
        :  - i.MX6UL GPIO clock gates in CCM CCGR
        clk: imx6ul: remove clks_init_on array
        clk: imx6ul: add GPIO clock gates
        dt-bindings: clock: imx6ul: Do not change the clock definition order
      5ef7748b
  2. 08 Aug, 2018 1 commit
  3. 06 Aug, 2018 1 commit
    • Levin Du's avatar
      clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 · 640332d1
      Levin Du authored
      PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
      RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
      from power on and the VDD_LOG is about 0.9V. When the kernel boots
      normally into the system, the PWM2 keeps outputing PWM signal.
      
      But the kernel hangs randomly after "Starting kernel ..." line on that
      board. When it happens, PWM2 outputs high level which causes VDD_LOG
      drops to 0.4V below the normal operating voltage.
      
      By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
      PWM clock is ensured to be prepared at startup and the PWM2 output is
      normal. After repeated tests, the early boot hang is gone.
      
      This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.
      Signed-off-by: default avatarLevin Du <djw@t-chip.com.cn>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      640332d1
  4. 11 Jul, 2018 1 commit
  5. 09 Jul, 2018 21 commits
  6. 08 Jul, 2018 1 commit
  7. 07 Jul, 2018 1 commit
  8. 06 Jul, 2018 9 commits