- 13 Jun, 2023 1 commit
-
-
Andrew Halaney authored
With wider usage on more boards, there have been reports of the following: [ 315.016174] qcom-ethqos 20000.ethernet eth0: no phy at addr -1 [ 315.016179] qcom-ethqos 20000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) which has been fairly random and isolated to specific boards. Early reports were written off as a hardware issue, but it has been prevalent enough on boards that theory seems unlikely. In bring up of a newer piece of hardware, similar was seen, but this time _consistently_. Moving the reset to the mdio bus level (which isn't exactly a lie, it is the only device on the bus so one could model it as such) fixed things on that platform. Analysis on sa8540p-ride shows that the phy's reset is not being handled during the OUI scan if the reset lives in the phy node: # gpio 752 is the reset, and is active low, first mdio reads are the OUI modprobe-420 [006] ..... 154.738544: mdio_access: stmmac-0 read phy:0x08 reg:0x02 val:0x0141 modprobe-420 [007] ..... 154.738665: mdio_access: stmmac-0 read phy:0x08 reg:0x03 val:0x0dd4 modprobe-420 [004] ..... 154.741357: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.741358: gpio_direction: 752 out (0) modprobe-420 [004] ..... 154.741360: gpio_value: 752 set 0 modprobe-420 [006] ..... 154.762751: gpio_value: 752 set 1 modprobe-420 [007] ..... 154.846857: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.937824: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-420 [004] ..... 154.937932: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 Moving it to the bus level, or specifying the OUI in the phy's compatible ensures the reset is handled before any mdio access Here is tracing with the OUI approach (which skips scanning the OUI): modprobe-549 [007] ..... 63.860295: gpio_value: 752 set 1 modprobe-549 [007] ..... 63.860297: gpio_direction: 752 out (0) modprobe-549 [007] ..... 63.860299: gpio_value: 752 set 0 modprobe-549 [004] ..... 63.882599: gpio_value: 752 set 1 modprobe-549 [005] ..... 63.962132: gpio_value: 752 set 1 modprobe-549 [006] ..... 64.049379: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-549 [006] ..... 64.049490: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 The OUI approach is taken given the description matches the situation perfectly (taken from ethernet-phy.yaml): - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: If the PHY reports an incorrect ID (or none at all) then the compatible list may contain an entry with the correct PHY ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, this is the chip vendor OUI bits 19:24, followed by 10 bits of a vendor specific ID. With this in place the sa8540p-ride's phy is probing consistently, so it seems the floating reset during mdio access was the issue. In either case, it shouldn't be floating so this improves the situation. The below link discusses some of the relationship of mdio, its phys, and points to this OUI compatible as a way to opt out of the OUI scan pre-reset handling which influenced this decision. Link: https://lore.kernel.org/all/dca54c57-a3bd-1147-63b2-4631194963f0@gmail.com/ Fixes: 57827e87 ("arm64: dts: qcom: sa8540p-ride: Add ethernet nodes") Signed-off-by:Andrew Halaney <ahalaney@redhat.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608201513.882950-1-ahalaney@redhat.com
-
- 30 May, 2023 10 commits
-
-
Bjorn Andersson authored
Introduce support for the Lenovo Flex 5G laptop, built on the Qualcomm SC8180X platform. Supported peripherals includes keyboard, touchpad, UFS storage, external USB and WiFi. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
-
Bjorn Andersson authored
Introduce support for the SC8180X reference device, aka Primus, with debug UART, regulators, UFS and USB support. Signed-off-by:
-
Vinod Koul authored
SC8180X based platforms have PM8150, PM8150C, PMC8180 and SMB2351 PMICs, so add these as well Co-developed-by:
-
Vinod Koul authored
This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with dsi0/1, dp0/1 and edp subnodes as found in this SoC Co-developed-by:
-
Vinod Koul authored
This patch adds remoteprocs, wifi and usb and usb phy nodes for this SoC Co-developed-by:
-
Vinod Koul authored
This patch adds PCIe instances found on this SoC Co-developed-by:
-
Vinod Koul authored
This patch adds qup instances and i2c, spi, serial ports Co-developed-by:
-
Vinod Koul authored
This patch adds tsens nodes and thermal zones for sc8180x SoC Co-developed-by:
-
Vinod Koul authored
This add interconnect nodes and add LMH to sc8180x SoC dtsi Co-developed-by:
-
Bjorn Andersson authored
Introduce a base dtsi for the Qualcomm SC8180x platform, with CPUs, global clock controller, SMMU, rpmh clocks, rpmh power-domains, CPUfreq etc Signed-off-by:
-
- 29 May, 2023 8 commits
-
-
Stephan Gerhold authored
MSM8939 has the aliases defined separately for each board (because there could be (theoretically) a board where the slots are numbered differently. To make MSM8916 and MSM8939 more consistent do the same for all MSM8916 boards and move aliases there. Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
-
Stephan Gerhold authored
All definitions in pm8916.dtsi use the &pm8916_ label prefix, only the codec uses the &wcd_codec label. &wcd_codec is confusing because the codec on MSM8916 is split into a "wcd-digital" and "wcd-analog" part and both could be described with &wcd_codec. Let's just name it &pm8916_codec so it's consistent with all other PMIC device nodes. Signed-off-by:
-
Stephan Gerhold authored
Right now MDSS related definitions cannot be properly grouped together in board DTs because the labels do not use consistent prefixes. The DSI PHY label is particularly weird because the DSI number is at the end (&dsi_phy0) while DSI itself is called &dsi0. Follow the example of more recent SoCs and give all the MDSS related nodes a consistent label that allows proper grouping. Signed-off-by:
-
Stephan Gerhold authored
Make the labels for the BLSP I2C/SPI pinctrl consistent with the one used for UART by adding the missing blsp_ prefix. This allows having them properly grouped together. The nodes are only reordered in msm8939.dtsi for now since the pinctrl definitions in msm8916-pins.dtsi are currently still unordered anyway. (I will try fixing this in a future patch.) Signed-off-by:
-
Stephan Gerhold authored
For some reason the BLSP UART controllers have a label with a number behind blsp (&blsp1_uartN) while I2C/SPI are named without (&blsp_i2cN). This is confusing, especially for proper node ordering in board DTs. Right now all board DTs are ordered as if the number behind blsp does not exist (&blsp_i2cN comes before &blsp1_uartN). Strictly speaking correct ordering would be the other way around ('1' comes before '_'). End this confusion by giving the UART controllers consistent labels. There is just one BLSP on MSM8916/39 so the number is redundant. Signed-off-by: -
Stephan Gerhold authored
MSM8916 is the only ARM64 Qualcomm SoC that is still using the old &msmgpio name. Change this to &tlmm to avoid confusion. Note that the node ordering does not change because the MSM8916 device trees have pinctrl separated at the bottom (similar to sc7180). Signed-off-by:
-
Bhupesh Sharma authored
Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
-
Bhupesh Sharma authored
Add USB superspeed qmp phy node to dtsi. Make sure that the various board dts files (which include sm4250.dtsi file) continue to work as intended. Reviewed-by:
-
- 27 May, 2023 11 commits
-
-
Kathiravan T authored
Add the initial device tree support for the Reference Design Platform(RDP) 442 based on IPQ5332 family of SoC. This patch carries the support for Console UART, SPI NOR, eMMC and I2C. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Kathiravan T authored
Document the MI01.3 (Reference Design Platform 442) board based on IPQ5332 family of SoCs. Signed-off-by:
-
Jagadeesh Kona authored
Add device node for graphics clock controller on Qualcomm SM8550 platform. Signed-off-by:
Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by:
-
Bjorn Andersson authored
Introduce DeviceTree bindings for SM8450 and SM8550 GPU clock controller, to introduce the constants necessary to referr to these clocks.
-
Jagadeesh Kona authored
Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
-
Konrad Dybcio authored
Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by:
-
Shazad Hussain authored
This enables the i2c11 node on sa8775p-ride board for A2B controller and audio port expander. Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by:
-
Shazad Hussain authored
Add remaining uart5 and uart9 nodes for UART bus present on sa8775p SoC. Signed-off-by:
-
Shazad Hussain authored
Add the missing nodes of the SPI buses present on sa8775p platform. Signed-off-by:
-
Shazad Hussain authored
Add the missing nodes for the i2c buses present on sa8775p Soc. Signed-off-by:
-
Shazad Hussain authored
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by:
-
- 26 May, 2023 10 commits
-
-
Krzysztof Kozlowski authored
Correct the typo in 'regulator-name' property. apq8096-ifc6640.dtb: v1p05-regulator: 'regulator-name' is a required property apq8096-ifc6640.dtb: v1p05-regulator: Unevaluated properties are not allowed ('reglator-name' was unexpected) Fixes: 6cbdec2d ("arm64: dts: qcom: msm8996: Introduce IFC6640") Signed-off-by: -
Krzysztof Kozlowski authored
Re-order the clocks for MMCC clock controller node to match the bindings (Linux driver takes by name): msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected Signed-off-by:
-
Krzysztof Kozlowski authored
Re-order the clocks for LPASS CPU node to match the bindings (Linux driver takes by name): msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:1: 'mi2s-bit-clk0' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:2: 'mi2s-bit-clk1' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:3: 'mi2s-bit-clk2' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:4: 'mi2s-bit-clk3' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:5: 'pcnoc-mport-clk' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:6: 'pcnoc-sway-clk' was expected Signed-off-by:
-
Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
-
Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
-
Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
-
Krzysztof Kozlowski authored
The bus@0 node should have reg or ranges to fix dtbs W=1 warnings: Warning (unit_address_vs_reg): /soc@0/bus@0: node has a unit name, but no reg or ranges property Warning (simple_bus_reg): /soc@0/bus@0: missing or empty reg/ranges property Signed-off-by:
-
Krzysztof Kozlowski authored
SoC DTSI already comes with 85800000 reserved memory node, so assume the author wanted to update its length. This fixes dtbs W=1 warning: Warning (unique_unit_address_if_enabled): /reserved-memory/qhee-code@85800000: duplicate unit-address (also used in node /reserved-memory/reserved@85800000) Signed-off-by:
-
Krzysztof Kozlowski authored
Bindings expect ADC channel node names to follow specific pattern: sm6125-xiaomi-laurel-sprout.dtb: adc@3100: 'adc-chan@4d', 'adc-chan@4e', 'adc-chan@52', 'adc-chan@54' do not match any of the regexes: ... Signed-off-by:
-
Krzysztof Kozlowski authored
The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards to define frequency. Use the same as in MTP8550 to fix: sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property Signed-off-by:
-
