- 18 Oct, 2022 36 commits
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Dmitry Baryshkov authored
Correct firmware paths for the Sony Xperia Sagami devices to include the SoC name, vendor and platform names. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919190037.2122284-5-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Correct firmware paths for the Inforce IFC6560 to include the SoC name. Do not include the platform name, since the board uses test-signed firmware. Signed-off-by:
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Dmitry Baryshkov authored
Correct firmware paths for the Lenovo Miix 630 to include the SoC name. Signed-off-by:
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Dmitry Baryshkov authored
Correct firmware paths for the Samsung Galaxy Book2 to include the SoC name. Signed-off-by:
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Joel Selvaraj authored
Introduce support for the Xiaomi Poco F1 EBBG variant. The EBBG variant uses EBBG FT8719 panel manufactured by EBBG. Signed-off-by:
Joel Selvaraj <joelselvaraj.oss@gmail.com> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Caleb Connolly <caleb@connolly.tech> Signed-off-by:
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Joel Selvaraj authored
Add documentation for "xiaomi,beryllium-ebbg" device. Signed-off-by:
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Joel Selvaraj authored
There are two panel variants of Xiaomi Poco F1. Tianma and EBBG panel. The previous beryllium dts supported the Tianma variant. In order to add support for EBBG variant, the common nodes from beryllium dts are moved to a new common dtsi and to make the variants distinguishable, sdm845-xiaomi-beryllium.dts is now named as sdm845-xiaomi-beryllium-tianma.dts. The model property is updated to distinguish between the variants. The compatibility property is moved to the tianma variant, but it is not updated to avoid any further conflict with other projects/users that might depend on it. Signed-off-by:
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Dmitry Baryshkov authored
Add device node for display clock controller on Qualcomm SM8450 platform Signed-off-by:
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Krzysztof Kozlowski authored
GPIO controller nodes are named by convention just "gpio", not "gpios". Signed-off-by:
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Rajeev Nandan authored
Assign DSI clock source parents to DSI PHY clocks. Signed-off-by:
Rajeev Nandan <quic_rajeevny@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sm8250 DSI controller block. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sdm845 DSI controller block. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sdm630 DSI controller block. Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sdm660 DSI controller block. Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sc7280 DSI controller block. Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the sc7180 DSI controller block. Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the msm8996 DSI controller block. Signed-off-by:
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Bryan O'Donoghue authored
phy-names has been marked deprecated. Remove it from the msm8916 DSI controller block. Signed-off-by:
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Krishna Kurapati authored
Overriding the SNPS Phy tuning parameters for SC7280 IDP device. Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by:
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Matthias Kaehlcke authored
The dwc3 USB controller of the sc7180 supports USB remote wakeup, configure it as a wakeup source. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Vladimir Zapolskiy authored
Add description of two CCI controllers found on QCOM SM8450. Signed-off-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by:
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Yunlong Jia authored
Create first version device tree for pazquel360 pazquel360 is convertible and the pazquel it is based on is clamshell. sku 20 for lte & wifi sku 21 for wifi only sku 22 for lte w/o esim & wifi Signed-off-by:
Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-by:
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Yunlong Jia authored
pazquel360 is an extension project based on pazquel. We create 3 sku on pazquel360: sku 20 for LTE with physical SIM _and_ eSIM and WiFi sku 21 for WiFi only sku 22 for LTE with only a physical SIM Both sku20 and sku22 are LTE SKUs. One has the eSIM stuffed and one doesn't. There is a single shared device tree for the two. Signed-off-by:
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Dmitry Baryshkov authored
Add displayport controller device node, describing DisplayPort hardware block on SDM845. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather than just usb phy. Signed-off-by:
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Stephan Gerhold authored
MSM8916 was originally using the "qcom,q6v5-pil" compatible for the MSS remoteproc. Later it was decided to use SoC-specific compatibles instead, so "qcom,msm8916-mss-pil" is now the preferred compatible. Commit 60a05ed0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") updated the MSM8916 device tree to make use of the new compatible but still kept the old "qcom,q6v5-pil" as fallback. This is inconsistent with other SoCs and conflicts with the description in the binding documentation (which says that only one compatible should be present). Also, it has no functional advantage since older kernels could not handle this DT anyway (e.g. "power-domains" in the MSS node is only supported by kernels that also support "qcom,msm8916-mss-pil"). Make this consistent with other SoCs by using only the "qcom,msm8916-mss-pil" compatible. Fixes: 60a05ed0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") Signed-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by:
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Krzysztof Kozlowski authored
Add missing space or remove redundant one before opening {. Signed-off-by:Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add a node for NXP PN553 NFC, using the nxp-nci driver. Signed-off-by:
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Krzysztof Kozlowski authored
There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: 79e7739f ("arm64: dts: qcom: sdm845-cheza: add initial cheza dt") Signed-off-by:
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Krzysztof Kozlowski authored
The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_spi2_default pin configuration uses alreaady the second method with a "pinmux" child, so configure drive-strength similarly in "pinconf". Otherwise the PIN drive strength would not be applied. Fixes: 8d23a004 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") Cc: <stable@vger.kernel.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: b190fb01 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Signed-off-by:
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Robert Marko authored
Since now we have control over the PMP8074 PMIC providing various system voltages including L11 which provides the SDIO/eMMC I/O voltage set it as the SDHCI VQMMC supply. This allows SDHCI controller to switch to 1.8V I/O mode and support high speed modes like HS200 and HS400. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is controlled via SPMI. Add DTSI for it providing GPIO, regulator, RTC and VADC support. RTC is disabled by default as there is no built-in battery so it will loose time unless board vendor added a battery, so make it optional. Signed-off-by:
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Robert Marko authored
APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the A53 PLL and XO clocks in order to use APCS as the CPU clocksource for APSS scaling. Signed-off-by:
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Bjorn Andersson authored
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Robert Marko authored
IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by:
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- 17 Oct, 2022 4 commits
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Dmitry Baryshkov authored
There are minor differeces between msm8996 and msm8996pro in terms of GPU frequencies support. For example msm8996pro supports 652.8 MHz frequency for the Adreno. Reclect these differences in msm8996pro.dtsi. Signed-off-by:
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Dmitry Baryshkov authored
Fix Adreno OPP table according to the msm-3.18. Enable 624 MHz for the speed bin 3 and 560 MHz for bins 2 and 3. Fixes: 69cc3114 ("arm64: dts: Add Adreno GPU definitions") Signed-off-by:
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Dmitry Baryshkov authored
Add support for msm8996, speed bin 3. It supports full range of frequencies on the power cluster, but is limited to 1.8 GHz on performance cluster. Signed-off-by:
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Dmitry Baryshkov authored
Adjust MSM8996 cpufreq tables according to tables in msm-3.18. Some of the frequencies are not supported on speed bins other than 0. Also other speed bins support intermediate topmost frequencies, not supported on speed bin 0. Implement all these differencies. Fixes: 90173a95 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by:
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