Commit cf377ad7 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Arnd Bergmann:
 "New and updated SoC support.  Among the things new for this release
  are:

   - at91: Added support for the new SAMA5D4 SoC, following the earlier
     SAMA5D3
   - bcm: Added support for BCM63XX family of DSL SoCs
   - hisi: Added support for HiP04 server-class SoC
   - meson: Initial support for the Amlogic Meson6 (aka 8726MX) platform
   - shmobile: added support for new r8a7794 (R-Car E2) automotive SoC

  Noteworthy changes to existing SoC support are:

   - imx: convert i.MX1 to device tree
   - omap: lots of power management work
   - omap: base support to enable moving to standard UART driver
   - shmobile: lots of progress for multiplatform support, still
     ongoing"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (171 commits)
  ARM: hisi: depend on ARCH_MULTI_V7
  CNS3xxx: Fix debug UART.
  ARM: at91: fix nommu build regression
  ARM: meson: add basic support for MesonX SoCs
  ARM: meson: debug: add debug UART for earlyprintk support
  irq: Export handle_fasteoi_irq
  ARM: mediatek: Add earlyprintk support for mt6589
  ARM: hisi: Fix platmcpm compilation when ARMv6 is selected
  ARM: debug: fix alphanumerical order on debug uarts
  ARM: at91: document Atmel SMART compatibles
  ARM: at91: add sama5d4 support to sama5_defconfig
  ARM: at91: dt: add device tree file for SAMA5D4ek board
  ARM: at91: dt: add device tree file for SAMA5D4 SoC
  ARM: at91: SAMA5D4 SoC detection code and low level routines
  ARM: at91: introduce basic SAMA5D4 support
  clk: at91: add a driver for the h32mx clock
  ARM: pxa3xx: provide specific platform_devices for all ssp ports
  ARM: pxa: ssp: provide platform_device_id for PXA3xx
  ARM: OMAP4+: Remove static iotable mappings for SRAM
  ARM: OMAP4+: Move SRAM data to DT
  ...
parents 212fe84a d8f0faa3
Atmel AT91 device tree bindings. Atmel AT91 device tree bindings.
================================ ================================
Boards with a SoC of the Atmel AT91 or SMART family shall have the following
properties:
Required root node properties:
compatible: must be one of:
* "atmel,at91rm9200"
* "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
the specific SoC family or compatible:
o "atmel,at91sam9260"
o "atmel,at91sam9261"
o "atmel,at91sam9263"
o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
SoC compatible:
- "atmel,at91sam9g15"
- "atmel,at91sam9g25"
- "atmel,at91sam9g35"
- "atmel,at91sam9x25"
- "atmel,at91sam9x35"
o "atmel,at91sam9g20"
o "atmel,at91sam9g45"
o "atmel,at91sam9n12"
o "atmel,at91sam9rl"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family:
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
- "atmel,sama5d31"
- "atmel,sama5d33"
- "atmel,sama5d34"
- "atmel,sama5d35"
- "atmel,sama5d36"
o "atmel,sama5d4" shall be extended with the specific SoC compatible:
- "atmel,sama5d41"
- "atmel,sama5d42"
- "atmel,sama5d43"
- "atmel,sama5d44"
PIT Timer required properties: PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit" - compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length - reg: Should contain registers location and length
......
Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
-----------------------------------------------------------
Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
following properties:
Required root node property:
compatible: should be "brcm,bcm63138"
...@@ -5,6 +5,11 @@ Hi4511 Board ...@@ -5,6 +5,11 @@ Hi4511 Board
Required root node properties: Required root node properties:
- compatible = "hisilicon,hi3620-hi4511"; - compatible = "hisilicon,hi3620-hi4511";
HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hip04-d01";
Hisilicon system controller Hisilicon system controller
Required properties: Required properties:
...@@ -55,3 +60,21 @@ Example: ...@@ -55,3 +60,21 @@ Example:
compatible = "hisilicon,pctrl"; compatible = "hisilicon,pctrl";
reg = <0xfca09000 0x1000>; reg = <0xfca09000 0x1000>;
}; };
-----------------------------------------------------------------------
Fabric:
Required Properties:
- compatible: "hisilicon,hip04-fabric";
- reg: Address and size of Fabric
-----------------------------------------------------------------------
Bootwrapper boot method (software protocol on SMP):
Required Properties:
- compatible: "hisilicon,hip04-bootwrapper";
- boot-method: Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
...@@ -10,6 +10,9 @@ Required properties: ...@@ -10,6 +10,9 @@ Required properties:
Should be "ti,omap5-mpu" for OMAP5 Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu" - ti,hwmods: "mpu"
Optional properties:
- sram: Phandle to the ocmcram node
Examples: Examples:
- For an OMAP5 SMP system: - For an OMAP5 SMP system:
......
NVIDIA Tegra Flow Controller
Required properties:
- compatible: Should be "nvidia,tegra<chip>-flowctrl"
- reg: Should contain one register range (address and length)
Example:
flow-controller@60007000 {
compatible = "nvidia,tegra20-flowctrl";
reg = <0x60007000 0x1000>;
};
...@@ -74,6 +74,9 @@ Required properties: ...@@ -74,6 +74,9 @@ Required properties:
"atmel,at91sam9x5-clk-utmi": "atmel,at91sam9x5-clk-utmi":
at91 utmi clock at91 utmi clock
"atmel,sama5d4-clk-h32mx":
at91 h32mx clock
Required properties for SCKC node: Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC. - reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id). - #size-cells : shall be 0 (reg is used to encode clk id).
...@@ -447,3 +450,14 @@ For example: ...@@ -447,3 +450,14 @@ For example:
#clock-cells = <0>; #clock-cells = <0>;
clocks = <&main>; clocks = <&main>;
}; };
Required properties for 32 bits bus Matrix clock (h32mx clock):
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock source phandle.
For example:
h32ck: h32mxck {
#clock-cells = <0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
};
...@@ -11,9 +11,11 @@ Required Properties: ...@@ -11,9 +11,11 @@ Required Properties:
- compatible: Must be one of the following - compatible: Must be one of the following
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
- reg: Base address and length of the I/O mapped registers used by the MSTP - reg: Base address and length of the I/O mapped registers used by the MSTP
clocks. The first register is the clock control register and is mandatory. clocks. The first register is the clock control register and is mandatory.
......
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area
Example:
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
...@@ -2065,6 +2065,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c ...@@ -2065,6 +2065,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c
F: arch/arm/boot/dts/bcm5301x.dtsi F: arch/arm/boot/dts/bcm5301x.dtsi
F: arch/arm/boot/dts/bcm470* F: arch/arm/boot/dts/bcm470*
BROADCOM BCM63XX ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
L: linux-arm-kernel@lists.infradead.org
T: git git://git.github.com/brcm/linux.git
S: Maintained
F: arch/arm/mach-bcm/bcm63xx.c
F: arch/arm/include/debug/bcm63xx.S
BROADCOM BCM7XXX ARM ARCHITECTURE BROADCOM BCM7XXX ARM ARCHITECTURE
M: Marc Carino <marc.ceeeee@gmail.com> M: Marc Carino <marc.ceeeee@gmail.com>
M: Brian Norris <computersforpeace@gmail.com> M: Brian Norris <computersforpeace@gmail.com>
......
...@@ -387,6 +387,7 @@ config ARCH_CLPS711X ...@@ -387,6 +387,7 @@ config ARCH_CLPS711X
select CPU_ARM720T select CPU_ARM720T
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select MFD_SYSCON select MFD_SYSCON
select SOC_BUS
help help
Support for Cirrus Logic 711x/721x/731x based boards. Support for Cirrus Logic 711x/721x/731x based boards.
...@@ -890,6 +891,8 @@ source "arch/arm/mach-keystone/Kconfig" ...@@ -890,6 +891,8 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig" source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-moxart/Kconfig" source "arch/arm/mach-moxart/Kconfig"
...@@ -1407,6 +1410,15 @@ config MCPM ...@@ -1407,6 +1410,15 @@ config MCPM
for (multi-)cluster based systems, such as big.LITTLE based for (multi-)cluster based systems, such as big.LITTLE based
systems. systems.
config MCPM_QUAD_CLUSTER
bool
depends on MCPM
help
To avoid wasting resources unnecessarily, MCPM only supports up
to 2 clusters by default.
Platforms with 3 or 4 clusters that use MCPM must select this
option to allow the additional clusters to be managed.
config BIG_LITTLE config BIG_LITTLE
bool "big.LITTLE support (Experimental)" bool "big.LITTLE support (Experimental)"
depends on CPU_V7 && SMP depends on CPU_V7 && SMP
......
...@@ -101,6 +101,10 @@ choice ...@@ -101,6 +101,10 @@ choice
bool "Kernel low-level debugging on 9263 and 9g45" bool "Kernel low-level debugging on 9263 and 9g45"
depends on HAVE_AT91_DBGU1 depends on HAVE_AT91_DBGU1
config AT91_DEBUG_LL_DBGU2
bool "Kernel low-level debugging on sama5d4"
depends on HAVE_AT91_DBGU2
config DEBUG_BCM2835 config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART" bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835 depends on ARCH_BCM2835
...@@ -122,6 +126,11 @@ choice ...@@ -122,6 +126,11 @@ choice
mobile SoCs in the Kona family of chips (e.g. bcm28155, mobile SoCs in the Kona family of chips (e.g. bcm28155,
bcm11351, etc...) bcm11351, etc...)
config DEBUG_BCM63XX
bool "Kernel low-level debugging on BCM63XX UART"
depends on ARCH_BCM_63XX
select DEBUG_UART_BCM63XX
config DEBUG_BERLIN_UART config DEBUG_BERLIN_UART
bool "Marvell Berlin SoC Debug UART" bool "Marvell Berlin SoC Debug UART"
depends on ARCH_BERLIN depends on ARCH_BERLIN
...@@ -223,14 +232,6 @@ choice ...@@ -223,14 +232,6 @@ choice
Say Y here if you want kernel low-level debugging support Say Y here if you want kernel low-level debugging support
on HI3716 UART. on HI3716 UART.
config DEBUG_HIX5HD2_UART
bool "Hisilicon Hix5hd2 Debug UART"
depends on ARCH_HIX5HD2
select DEBUG_UART_PL01X
help
Say Y here if you want kernel low-level debugging support
on Hix5hd2 UART.
config DEBUG_HIGHBANK_UART config DEBUG_HIGHBANK_UART
bool "Kernel low-level debugging messages via Highbank UART" bool "Kernel low-level debugging messages via Highbank UART"
depends on ARCH_HIGHBANK depends on ARCH_HIGHBANK
...@@ -239,6 +240,22 @@ choice ...@@ -239,6 +240,22 @@ choice
Say Y here if you want the debug print routines to direct Say Y here if you want the debug print routines to direct
their output to the UART on Highbank based devices. their output to the UART on Highbank based devices.
config DEBUG_HIP04_UART
bool "Hisilicon HiP04 Debug UART"
depends on ARCH_HIP04
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on HIP04 UART.
config DEBUG_HIX5HD2_UART
bool "Hisilicon Hix5hd2 Debug UART"
depends on ARCH_HIX5HD2
select DEBUG_UART_PL01X
help
Say Y here if you want kernel low-level debugging support
on Hix5hd2 UART.
config DEBUG_IMX1_UART config DEBUG_IMX1_UART
bool "i.MX1 Debug UART" bool "i.MX1 Debug UART"
depends on SOC_IMX1 depends on SOC_IMX1
...@@ -348,6 +365,13 @@ choice ...@@ -348,6 +365,13 @@ choice
Say Y here if you want the debug print routines to direct Say Y here if you want the debug print routines to direct
their output to UART1 serial port on KEYSTONE2 devices. their output to UART1 serial port on KEYSTONE2 devices.
config DEBUG_MESON_UARTAO
bool "Kernel low-level debugging via Meson6 UARTAO"
depends on ARCH_MESON
help
Say Y here if you want kernel low-lever debugging support
on Amlogic Meson6 based platforms on the UARTAO.
config DEBUG_MMP_UART2 config DEBUG_MMP_UART2
bool "Kernel low-level debugging message via MMP UART2" bool "Kernel low-level debugging message via MMP UART2"
depends on ARCH_MMP depends on ARCH_MMP
...@@ -834,6 +858,14 @@ choice ...@@ -834,6 +858,14 @@ choice
Say Y here if you want kernel low-level debugging support Say Y here if you want kernel low-level debugging support
on Ux500 based platforms. on Ux500 based platforms.
config DEBUG_MT6589_UART0
bool "Mediatek mt6589 UART0"
depends on ARCH_MEDIATEK
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
for Mediatek mt6589 based platforms on UART0.
config DEBUG_VEXPRESS_UART0_DETECT config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU depends on ARCH_VEXPRESS && CPU_CP15_MMU
...@@ -1011,6 +1043,7 @@ config DEBUG_LL_INCLUDE ...@@ -1011,6 +1043,7 @@ config DEBUG_LL_INCLUDE
string string
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
default "debug/meson.S" if DEBUG_MESON_UARTAO
default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
default "debug/exynos.S" if DEBUG_EXYNOS_UART default "debug/exynos.S" if DEBUG_EXYNOS_UART
default "debug/efm32.S" if DEBUG_LL_UART_EFM32 default "debug/efm32.S" if DEBUG_LL_UART_EFM32
...@@ -1038,6 +1071,7 @@ config DEBUG_LL_INCLUDE ...@@ -1038,6 +1071,7 @@ config DEBUG_LL_INCLUDE
default "debug/vf.S" if DEBUG_VF_UART default "debug/vf.S" if DEBUG_VF_UART
default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/vt8500.S" if DEBUG_VT8500_UART0
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX
default "mach/debug-macro.S" default "mach/debug-macro.S"
# Compatibility options for PL01x # Compatibility options for PL01x
...@@ -1057,6 +1091,10 @@ config DEBUG_UART_8250 ...@@ -1057,6 +1091,10 @@ config DEBUG_UART_8250
ARCH_IOP33X || ARCH_IXP4XX || \ ARCH_IOP33X || ARCH_IXP4XX || \
ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
# Compatibility options for BCM63xx
config DEBUG_UART_BCM63XX
def_bool ARCH_BCM_63XX
config DEBUG_UART_PHYS config DEBUG_UART_PHYS
hex "Physical base address of debug UART" hex "Physical base address of debug UART"
default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
...@@ -1075,6 +1113,7 @@ config DEBUG_UART_PHYS ...@@ -1075,6 +1113,7 @@ config DEBUG_UART_PHYS
default 0x10126000 if DEBUG_RK3X_UART1 default 0x10126000 if DEBUG_RK3X_UART1
default 0x101f1000 if ARCH_VERSATILE default 0x101f1000 if ARCH_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART default 0x101fb000 if DEBUG_NOMADIK_UART
default 0x11006000 if DEBUG_MT6589_UART0
default 0x16000000 if ARCH_INTEGRATOR default 0x16000000 if ARCH_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X default 0x18000300 if DEBUG_BCM_5301X
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
...@@ -1093,6 +1132,7 @@ config DEBUG_UART_PHYS ...@@ -1093,6 +1132,7 @@ config DEBUG_UART_PHYS
DEBUG_S3C2410_UART1) DEBUG_S3C2410_UART1)
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2) DEBUG_S3C2410_UART2)
default 0x78000000 if DEBUG_CNS3XXX
default 0x7c0003f8 if FOOTBRIDGE default 0x7c0003f8 if FOOTBRIDGE
default 0x78000000 if DEBUG_CNS3XXX default 0x78000000 if DEBUG_CNS3XXX
default 0x80070000 if DEBUG_IMX23_UART default 0x80070000 if DEBUG_IMX23_UART
...@@ -1107,9 +1147,11 @@ config DEBUG_UART_PHYS ...@@ -1107,9 +1147,11 @@ config DEBUG_UART_PHYS
default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
default 0xd0012000 if DEBUG_MVEBU_UART default 0xd0012000 if DEBUG_MVEBU_UART
default 0xc81004c0 if DEBUG_MESON_UARTAO
default 0xd4017000 if DEBUG_MMP_UART2 default 0xd4017000 if DEBUG_MMP_UART2
default 0xd4018000 if DEBUG_MMP_UART3 default 0xd4018000 if DEBUG_MMP_UART3
default 0xe0000000 if ARCH_SPEAR13XX default 0xe0000000 if ARCH_SPEAR13XX
default 0xe4007000 if DEBUG_HIP04_UART
default 0xf0000be0 if ARCH_EBSA110 default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \ default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
...@@ -1123,11 +1165,13 @@ config DEBUG_UART_PHYS ...@@ -1123,11 +1165,13 @@ config DEBUG_UART_PHYS
default 0xffc02000 if DEBUG_SOCFPGA_UART default 0xffc02000 if DEBUG_SOCFPGA_UART
default 0xffd82340 if ARCH_IOP13XX default 0xffd82340 if ARCH_IOP13XX
default 0xfff36000 if DEBUG_HIGHBANK_UART default 0xfff36000 if DEBUG_HIGHBANK_UART
default 0xfffe8600 if DEBUG_UART_BCM63XX
default 0xfffff700 if ARCH_IOP33X default 0xfffff700 if ARCH_IOP33X
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \ DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_UART_BCM63XX
config DEBUG_UART_VIRT config DEBUG_UART_VIRT
hex "Virtual base address of debug UART" hex "Virtual base address of debug UART"
...@@ -1137,6 +1181,7 @@ config DEBUG_UART_VIRT ...@@ -1137,6 +1181,7 @@ config DEBUG_UART_VIRT
default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835 default 0xf0201000 if DEBUG_BCM2835
default 0xf1000300 if DEBUG_BCM_5301X default 0xf1000300 if DEBUG_BCM_5301X
default 0xf1006000 if DEBUG_MT6589_UART0
default 0xf11f1000 if ARCH_VERSATILE default 0xf11f1000 if ARCH_VERSATILE
default 0xf1600000 if ARCH_INTEGRATOR default 0xf1600000 if ARCH_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0 default 0xf1c28000 if DEBUG_SUNXI_UART0
...@@ -1152,17 +1197,20 @@ config DEBUG_UART_VIRT ...@@ -1152,17 +1197,20 @@ config DEBUG_UART_VIRT
default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2) DEBUG_S3C2410_UART2)
default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8007000 if DEBUG_HIP04_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xfa71e000 if DEBUG_QCOM_UARTDM default 0xfa71e000 if DEBUG_QCOM_UARTDM
default 0xfb002000 if DEBUG_CNS3XXX default 0xfb002000 if DEBUG_CNS3XXX
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfcfe8600 if DEBUG_UART_BCM63XX
default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
default 0xfd000000 if ARCH_SPEAR13XX default 0xfd000000 if ARCH_SPEAR13XX
default 0xfd012000 if ARCH_MV78XX0 default 0xfd012000 if ARCH_MV78XX0
default 0xfde12000 if ARCH_DOVE default 0xfde12000 if ARCH_DOVE
default 0xfe012000 if ARCH_ORION5X default 0xfe012000 if ARCH_ORION5X
default 0xf31004c0 if DEBUG_MESON_UARTAO
default 0xfe017000 if DEBUG_MMP_UART2 default 0xfe017000 if DEBUG_MMP_UART2
default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
...@@ -1194,8 +1242,9 @@ config DEBUG_UART_VIRT ...@@ -1194,8 +1242,9 @@ config DEBUG_UART_VIRT
default 0xff003000 if DEBUG_U300_UART default 0xff003000 if DEBUG_U300_UART
default DEBUG_UART_PHYS if !MMU default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_UART_BCM63XX
config DEBUG_UART_8250_SHIFT config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART" int "Register offset shift for the 8250 debug UART"
......
...@@ -169,6 +169,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx ...@@ -169,6 +169,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KS8695) += ks8695 machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MSM) += msm machine-$(CONFIG_ARCH_MSM) += msm
......
...@@ -48,11 +48,14 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb ...@@ -48,11 +48,14 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
# sama5d4
dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
bcm21664-garnet.dtb bcm21664-garnet.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BERLIN) += \
...@@ -90,6 +93,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb ...@@ -90,6 +93,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb ecx-2000.dtb
dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb integratorcp.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
...@@ -361,7 +365,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ ...@@ -361,7 +365,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \ r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \ r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \ r8a7778-bockw-reference.dtb \
r8a7740-armadillo800eva-reference.dtb \
r8a7779-marzen.dtb \ r8a7779-marzen.dtb \
r8a7791-koelsch.dtb \ r8a7791-koelsch.dtb \
r8a7790-lager.dtb \ r8a7790-lager.dtb \
...@@ -372,6 +375,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ ...@@ -372,6 +375,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
sh7372-mackerel.dtb sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \ r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \
r8a7791-henninger.dtb \ r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \ r8a7791-koelsch.dtb \
r8a7790-lager.dtb \ r8a7790-lager.dtb \
......
...@@ -726,9 +726,8 @@ phy_sel: cpsw-phy-sel@44e10650 { ...@@ -726,9 +726,8 @@ phy_sel: cpsw-phy-sel@44e10650 {
}; };
ocmcram: ocmcram@40300000 { ocmcram: ocmcram@40300000 {
compatible = "ti,am3352-ocmcram"; compatible = "mmio-sram";
reg = <0x40300000 0x10000>; reg = <0x40300000 0x10000>; /* 64k */
ti,hwmods = "ocmcram";
}; };
wkup_m3: wkup_m3@44d00000 { wkup_m3: wkup_m3@44d00000 {
......
...@@ -885,6 +885,11 @@ rfbi: rfbi@4832a800 { ...@@ -885,6 +885,11 @@ rfbi: rfbi@4832a800 {
clock-names = "fck"; clock-names = "fck";
}; };
}; };
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */
};
}; };
}; };
......
/*
* at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
*
* Copyright (C) 2014 Atmel,
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d4.dtsi"
/ {
model = "Atmel SAMA5D4-EK";
compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
lcd_bus@f0000000 {
status = "okay";
lcd@f0000000 {
status = "okay";
};
lcdovl1@f0000140 {
status = "okay";
};
lcdovl2@f0000240 {
status = "okay";
};
lcdheo1@f0000340 {
status = "okay";
};
};
adc0: adc@fc034000 {
/* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
atmel,adc-vref = <3300>;
/*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
status = "okay"; /* Enable ADC IIO support */
};
mmc0: mmc@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
slot@1 {
reg = <1>;
bus-width = <4>;
cd-gpios = <&pioE 5 0>;
};
};
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
m25p80@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
i2c0: i2c@f8014000 {
status = "okay";
};
macb0: ethernet@f8020000 {
phy-mode = "rmii";
status = "okay";
};
mmc1: mmc@fc000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 6 0>;
};
};
usart2: serial@fc008000 {
status = "okay";
};
usart3: serial@fc00c000 {
status = "okay";
};
usart4: serial@fc010000 {
status = "okay";
};
watchdog@fc068640 {
status = "okay";
};
pinctrl@fc06a000 {
board {
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc1_cd: mmc1_cd {
atmel,pins =
<AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
};
};
};
};
usb0: gadget@00400000 {
atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00500000 {
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
&pioE 11 GPIO_ACTIVE_LOW
&pioE 12 GPIO_ACTIVE_LOW
>;
status = "okay";
};
usb2: ehci@00600000 {
status = "okay";
};
nand0: nand@80000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
atmel,has-pmecc;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
pb_user1 {
label = "pb_user1";
gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
};
/*
* Broadcom BCM63138 DSL SoCs Device Tree
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
/ {
compatible = "brcm,bcm63138";
model = "Broadcom BCM63138 DSL SoC";
interrupt-parent = <&gic>;
aliases {
uart0 = &serial0;
uart1 = &serial1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <1>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
};
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "periph";
};
};
/* ARM bus */
axi@80000000 {
compatible = "simple-bus";
ranges = <0 0x80000000 0x784000>;
#address-cells = <1>;
#size-cells = <1>;
L2: cache-controller@1d000 {
compatible = "arm,pl310-cache";
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-sets = <16>;
cache-size = <0x80000>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
scu: scu@1e000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1e000 0x100>;
};
gic: interrupt-controller@1e100 {
compatible = "arm,cortex-a9-gic";
reg = <0x1f000 0x1000
0x1e100 0x100>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
};
global_timer: timer@1e200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&arm_timer_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&arm_timer_clk>;
};
twd_watchdog: watchdog@1e620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x1e620 0x20>;
interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
};
};
/* Legacy UBUS base */
ubus@fffe8000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8100>;
serial0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
interrupts = <GIC_SPI 32 0>;
clocks = <&periph_clk>;
clock-names = "periph";
status = "disabled";
};
serial1: serial@620 {
compatible = "brcm,bcm6345-uart";
reg = <0x620 0x1b>;
interrupts = <GIC_SPI 33 0>;
clocks = <&periph_clk>;
clock-names = "periph";
status = "disabled";
};
};
};
/*
* Broadcom BCM63138 Reference Board DTS
*/
/dts-v1/;
#include "bcm63138.dtsi"
/ {
compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
model = "Broadcom BCM963138DVT";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &serial0;
};
memory {
reg = <0x0 0x08000000>;
};
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
...@@ -89,6 +89,7 @@ ocp { ...@@ -89,6 +89,7 @@ ocp {
prm: prm@4ae06000 { prm: prm@4ae06000 {
compatible = "ti,dra7-prm"; compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>; reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks { prm_clocks: clocks {
#address-cells = <1>; #address-cells = <1>;
......
/*
* Copyright (C) 2013-2014 Linaro Ltd.
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
#include "hip04.dtsi"
/ {
/* memory bus is 64-bit */
#address-cells = <2>;
#size-cells = <2>;
model = "Hisilicon D01 Development Board";
compatible = "hisilicon,hip04-d01";
memory@00000000,10000000 {
device_type = "memory";
reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
<0x00000004 0xc0000000 0x00000003 0x40000000>;
};
soc {
uart0: uart@4007000 {
status = "ok";
};
};
};
/*
* Hisilicon Ltd. HiP04 SoC
*
* Copyright (C) 2013-2014 Hisilicon Ltd.
* Copyright (C) 2013-2014 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* memory bus is 64-bit */
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
bootwrapper {
compatible = "hisilicon,hip04-bootwrapper";
boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
cluster2 {
core0 {
cpu = <&CPU8>;
};
core1 {
cpu = <&CPU9>;
};
core2 {
cpu = <&CPU10>;
};
core3 {
cpu = <&CPU11>;
};
};
cluster3 {
core0 {
cpu = <&CPU12>;
};
core1 {
cpu = <&CPU13>;
};
core2 {
cpu = <&CPU14>;
};
core3 {
cpu = <&CPU15>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x100>;
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x101>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x102>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x103>;
};
CPU8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x200>;
};
CPU9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x201>;
};
CPU10: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x202>;
};
CPU11: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x203>;
};
CPU12: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x300>;
};
CPU13: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x301>;
};
CPU14: cpu@302 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x302>;
};
CPU15: cpu@303 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x303>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
clk_50m: clk_50m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clk_168m: clk_168m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <168000000>;
};
soc {
/* It's a 32-bit SoC. */
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0 0xe0000000 0x10000000>;
gic: interrupt-controller@c01000 {
compatible = "hisilicon,hip04-intc";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
<0xc04000 0x2000>, <0xc06000 0x2000>;
};
sysctrl: sysctrl {
compatible = "hisilicon,sysctrl";
reg = <0x3e00000 0x00100000>;
};
fabric: fabric {
compatible = "hisilicon,hip04-fabric";
reg = <0x302a000 0x1000>;
};
dual_timer0: dual_timer@3000000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
clocks = <&clk_50m>, <&clk_50m>;
clock-names = "apb_pclk";
};
arm-pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 64 4>,
<0 65 4>,
<0 66 4>,
<0 67 4>,
<0 68 4>,
<0 69 4>,
<0 70 4>,
<0 71 4>,
<0 72 4>,
<0 73 4>,
<0 74 4>,
<0 75 4>,
<0 76 4>,
<0 77 4>,
<0 78 4>,
<0 79 4>;
};
uart0: uart@4007000 {
compatible = "snps,dw-apb-uart";
reg = <0x4007000 0x1000>;
interrupts = <0 381 4>;
clocks = <&clk_168m>;
clock-names = "uartclk";
reg-shift = <2>;
status = "disabled";
};
sata0: sata@a000000 {
compatible = "hisilicon,hisi-ahci";
reg = <0xa000000 0x1000000>;
interrupts = <0 372 4>;
};
};
};
...@@ -97,6 +97,7 @@ aes: aes@480c5000 { ...@@ -97,6 +97,7 @@ aes: aes@480c5000 {
prm: prm@48306000 { prm: prm@48306000 {
compatible = "ti,omap3-prm"; compatible = "ti,omap3-prm";
reg = <0x48306000 0x4000>; reg = <0x48306000 0x4000>;
interrupts = <11>;
prm_clocks: clocks { prm_clocks: clocks {
#address-cells = <1>; #address-cells = <1>;
......
...@@ -81,6 +81,7 @@ soc { ...@@ -81,6 +81,7 @@ soc {
mpu { mpu {
compatible = "ti,omap4-mpu"; compatible = "ti,omap4-mpu";
ti,hwmods = "mpu"; ti,hwmods = "mpu";
sram = <&ocmcram>;
}; };
dsp { dsp {
...@@ -129,6 +130,7 @@ cm1_clockdomains: clockdomains { ...@@ -129,6 +130,7 @@ cm1_clockdomains: clockdomains {
prm: prm@4a306000 { prm: prm@4a306000 {
compatible = "ti,omap4-prm"; compatible = "ti,omap4-prm";
reg = <0x4a306000 0x3000>; reg = <0x4a306000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks { prm_clocks: clocks {
#address-cells = <1>; #address-cells = <1>;
...@@ -208,6 +210,11 @@ pbias_mmc_reg: pbias_mmc_omap4 { ...@@ -208,6 +210,11 @@ pbias_mmc_reg: pbias_mmc_omap4 {
}; };
}; };
ocmcram: ocmcram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
};
sdma: dma-controller@4a056000 { sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma"; compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>; reg = <0x4a056000 0x1000>;
......
...@@ -104,8 +104,9 @@ gic: interrupt-controller@48211000 { ...@@ -104,8 +104,9 @@ gic: interrupt-controller@48211000 {
soc { soc {
compatible = "ti,omap-infra"; compatible = "ti,omap-infra";
mpu { mpu {
compatible = "ti,omap5-mpu"; compatible = "ti,omap4-mpu";
ti,hwmods = "mpu"; ti,hwmods = "mpu";
sram = <&ocmcram>;
}; };
}; };
...@@ -131,6 +132,7 @@ ocp { ...@@ -131,6 +132,7 @@ ocp {
prm: prm@4ae06000 { prm: prm@4ae06000 {
compatible = "ti,omap5-prm"; compatible = "ti,omap5-prm";
reg = <0x4ae06000 0x3000>; reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks { prm_clocks: clocks {
#address-cells = <1>; #address-cells = <1>;
...@@ -219,6 +221,11 @@ pbias_mmc_reg: pbias_mmc_omap5 { ...@@ -219,6 +221,11 @@ pbias_mmc_reg: pbias_mmc_omap5 {
}; };
}; };
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x20000>; /* 128k */
};
sdma: dma-controller@4a056000 { sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma"; compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>; reg = <0x4a056000 0x1000>;
......
...@@ -43,6 +43,10 @@ &usb_x1_clk { ...@@ -43,6 +43,10 @@ &usb_x1_clk {
clock-frequency = <48000000>; clock-frequency = <48000000>;
}; };
&mtu2 {
status = "ok";
};
&i2c2 { &i2c2 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -229,6 +229,16 @@ i2c3: i2c@fcfeec00 { ...@@ -229,6 +229,16 @@ i2c3: i2c@fcfeec00 {
status = "disabled"; status = "disabled";
}; };
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
status = "disabled";
};
scif0: serial@e8007000 { scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>; reg = <0xe8007000 64>;
......
/*
* Reference Device Tree Source for the armadillo 800 eva board
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7740.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "armadillo 800 eva reference";
compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
aliases {
serial1 = &scifa1;
};
chosen {
bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vcc_sdhi0: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator@2 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sdhi0>;
enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
states = <3300000 0
1800000 1>;
enable-active-high;
};
reg_5p0v: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "fixed-5.0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "SW3";
gpio-key,wakeup;
};
back-key {
gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "SW4";
};
menu-key {
gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
label = "SW5";
};
home-key {
gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "SW6";
};
};
leds {
compatible = "gpio-leds";
led3 {
gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
led4 {
gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
label = "LED4";
};
led5 {
gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
label = "LED5";
};
led6 {
gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
label = "LED6";
};
};
i2c2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
&pfc 91 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <5>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
default-brightness-level = <9>;
pinctrl-0 = <&backlight_pins>;
pinctrl-names = "default";
power-supply = <&reg_5p0v>;
enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,cpu {
sound-dai = <&sh_fsi2 0>;
bitclock-inversion;
};
simple-audio-card,codec {
sound-dai = <&wm8978>;
bitclock-master;
frame-master;
system-clock-frequency = <12288000>;
};
};
};
&ether {
pinctrl-0 = <&ether_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
status = "ok";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&i2c0 {
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
interrupt-parent = <&irqpin1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&st1232_pins>;
pinctrl-names = "default";
gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
};
wm8978: wm8978@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8978";
reg = <0x1a>;
};
};
&i2c2 {
status = "okay";
rtc@30 {
compatible = "sii,s35390a";
reg = <0x30>;
};
};
&pfc {
ether_pins: ether {
renesas,groups = "gether_mii", "gether_int";
renesas,function = "gether";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
};
st1232_pins: touchscreen {
renesas,groups = "intc_irq10";
renesas,function = "intc";
};
backlight_pins: backlight {
renesas,groups = "tpu0_to2_1";
renesas,function = "tpu0";
};
mmc0_pins: mmc0 {
renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
renesas,function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
renesas,function = "sdhi0";
};
fsia_pins: sounda {
renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
renesas,function = "fsia";
};
};
&tpu {
status = "okay";
};
&mmcif0 {
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scifa1 {
pinctrl-0 = <&scifa1_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sh_fsi2 {
pinctrl-0 = <&fsia_pins>;
pinctrl-names = "default";
status = "okay";
};
...@@ -10,10 +10,18 @@ ...@@ -10,10 +10,18 @@
/dts-v1/; /dts-v1/;
#include "r8a7740.dtsi" #include "r8a7740.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ { / {
model = "armadillo 800 eva"; model = "armadillo 800 eva";
compatible = "renesas,armadillo800eva"; compatible = "renesas,armadillo800eva", "renesas,r8a7740";
aliases {
serial1 = &scifa1;
};
chosen { chosen {
bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
...@@ -23,4 +31,270 @@ memory { ...@@ -23,4 +31,270 @@ memory {
device_type = "memory"; device_type = "memory";
reg = <0x40000000 0x20000000>; reg = <0x40000000 0x20000000>;
}; };
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vcc_sdhi0: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator@2 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sdhi0>;
enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
states = <3300000 0
1800000 1>;
enable-active-high;
};
reg_5p0v: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "fixed-5.0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "SW3";
gpio-key,wakeup;
};
back-key {
gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "SW4";
};
menu-key {
gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
label = "SW5";
};
home-key {
gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "SW6";
};
};
leds {
compatible = "gpio-leds";
led3 {
gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
led4 {
gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
label = "LED4";
};
led5 {
gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
label = "LED5";
};
led6 {
gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
label = "LED6";
};
};
i2c2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
&pfc 91 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <5>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
default-brightness-level = <9>;
pinctrl-0 = <&backlight_pins>;
pinctrl-names = "default";
power-supply = <&reg_5p0v>;
enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,cpu {
sound-dai = <&sh_fsi2 0>;
bitclock-inversion;
};
simple-audio-card,codec {
sound-dai = <&wm8978>;
bitclock-master;
frame-master;
system-clock-frequency = <12288000>;
};
};
};
&ether {
pinctrl-0 = <&ether_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
status = "ok";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&extal1_clk {
clock-frequency = <25000000>;
};
&extal2_clk {
clock-frequency = <48000000>;
};
&fsibck_clk {
clock-frequency = <12288000>;
};
&cpg_clocks {
renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
};
&cmt1 {
status = "ok";
};
&i2c0 {
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
interrupt-parent = <&irqpin1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&st1232_pins>;
pinctrl-names = "default";
gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
};
wm8978: wm8978@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8978";
reg = <0x1a>;
};
};
&i2c2 {
status = "okay";
rtc@30 {
compatible = "sii,s35390a";
reg = <0x30>;
};
};
&pfc {
ether_pins: ether {
renesas,groups = "gether_mii", "gether_int";
renesas,function = "gether";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
};
st1232_pins: touchscreen {
renesas,groups = "intc_irq10";
renesas,function = "intc";
};
backlight_pins: backlight {
renesas,groups = "tpu0_to2_1";
renesas,function = "tpu0";
};
mmc0_pins: mmc0 {
renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
renesas,function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
renesas,function = "sdhi0";
};
fsia_pins: sounda {
renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
renesas,function = "fsia";
};
};
&tpu {
status = "okay";
};
&mmcif0 {
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scifa1 {
pinctrl-0 = <&scifa1_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sh_fsi2 {
pinctrl-0 = <&fsia_pins>;
pinctrl-names = "default";
status = "okay";
}; };
This diff is collapsed.
...@@ -23,8 +23,14 @@ / { ...@@ -23,8 +23,14 @@ / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
cpus { cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 { cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <800000000>;
}; };
}; };
......
...@@ -78,6 +78,10 @@ &extal_clk { ...@@ -78,6 +78,10 @@ &extal_clk {
clock-frequency = <31250000>; clock-frequency = <31250000>;
}; };
&tmu0 {
status = "okay";
};
&pfc { &pfc {
lan0_pins: lan0 { lan0_pins: lan0 {
intc { intc {
......
...@@ -266,6 +266,48 @@ thermal@ffc48000 { ...@@ -266,6 +266,48 @@ thermal@ffc48000 {
reg = <0xffc48000 0x38>; reg = <0xffc48000 0x38>;
}; };
tmu0: timer@ffd80000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd80000 0x30>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
<0 33 IRQ_TYPE_LEVEL_HIGH>,
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
#renesas,channels = <3>;
status = "disabled";
};
tmu1: timer@ffd81000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd81000 0x30>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
<0 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
#renesas,channels = <3>;
status = "disabled";
};
tmu2: timer@ffd82000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd82000 0x30>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
<0 41 IRQ_TYPE_LEVEL_HIGH>,
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
#renesas,channels = <3>;
status = "disabled";
};
sata: sata@fc600000 { sata: sata@fc600000 {
compatible = "renesas,rcar-sata"; compatible = "renesas,rcar-sata";
reg = <0xfc600000 0x2000>; reg = <0xfc600000 0x2000>;
......
...@@ -252,6 +252,10 @@ phy1: ethernet-phy@1 { ...@@ -252,6 +252,10 @@ phy1: ethernet-phy@1 {
}; };
}; };
&cmt0 {
status = "ok";
};
&mmcif1 { &mmcif1 {
pinctrl-0 = <&mmc1_pins>; pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
...@@ -206,6 +206,38 @@ timer { ...@@ -206,6 +206,38 @@ timer {
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
<0 121 IRQ_TYPE_LEVEL_HIGH>,
<0 122 IRQ_TYPE_LEVEL_HIGH>,
<0 123 IRQ_TYPE_LEVEL_HIGH>,
<0 124 IRQ_TYPE_LEVEL_HIGH>,
<0 125 IRQ_TYPE_LEVEL_HIGH>,
<0 126 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
renesas,channels-mask = <0xff>;
status = "disabled";
};
irqc0: interrupt-controller@e61c0000 { irqc0: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7790", "renesas,irqc"; compatible = "renesas,irqc-r8a7790", "renesas,irqc";
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
...@@ -302,6 +302,10 @@ phy1: ethernet-phy@1 { ...@@ -302,6 +302,10 @@ phy1: ethernet-phy@1 {
}; };
}; };
&cmt0 {
status = "ok";
};
&sata0 { &sata0 {
status = "okay"; status = "okay";
}; };
......
...@@ -189,6 +189,38 @@ timer { ...@@ -189,6 +189,38 @@ timer {
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
<0 121 IRQ_TYPE_LEVEL_HIGH>,
<0 122 IRQ_TYPE_LEVEL_HIGH>,
<0 123 IRQ_TYPE_LEVEL_HIGH>,
<0 124 IRQ_TYPE_LEVEL_HIGH>,
<0 125 IRQ_TYPE_LEVEL_HIGH>,
<0 126 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
renesas,channels-mask = <0xff>;
status = "disabled";
};
irqc0: interrupt-controller@e61c0000 { irqc0: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7791", "renesas,irqc"; compatible = "renesas,irqc-r8a7791", "renesas,irqc";
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
This diff is collapsed.
...@@ -21,6 +21,7 @@ cpu@0 { ...@@ -21,6 +21,7 @@ cpu@0 {
compatible = "arm,cortex-a8"; compatible = "arm,cortex-a8";
device_type = "cpu"; device_type = "cpu";
reg = <0x0>; reg = <0x0>;
clock-frequency = <800000000>;
}; };
}; };
......
...@@ -173,6 +173,10 @@ simple-audio-card,codec { ...@@ -173,6 +173,10 @@ simple-audio-card,codec {
}; };
}; };
&cmt1 {
status = "ok";
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
as3711@40 { as3711@40 {
......
...@@ -23,11 +23,13 @@ cpu@0 { ...@@ -23,11 +23,13 @@ cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>; reg = <0>;
clock-frequency = <1196000000>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <1>; reg = <1>;
clock-frequency = <1196000000>;
}; };
}; };
...@@ -45,6 +47,16 @@ pmu { ...@@ -45,6 +47,16 @@ pmu {
<0 56 IRQ_TYPE_LEVEL_HIGH>; <0 56 IRQ_TYPE_LEVEL_HIGH>;
}; };
cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
reg = <0xe6138000 0x200>;
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
renesas,channels-mask = <0x3f>;
status = "disabled";
};
irqpin0: irqpin@e6900000 { irqpin0: irqpin@e6900000 {
compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
...@@ -146,6 +146,11 @@ L2: cache-controller { ...@@ -146,6 +146,11 @@ L2: cache-controller {
cache-level = <2>; cache-level = <2>;
}; };
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
} ;
uart0: serial@e0000000 { uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8"; compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled"; status = "disabled";
......
...@@ -68,8 +68,8 @@ CONFIG_GPIO_GENERIC_PLATFORM=y ...@@ -68,8 +68,8 @@ CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_HWMON is not set # CONFIG_HWMON is not set
CONFIG_FB=y CONFIG_FB=y
CONFIG_FB_CLPS711X=y CONFIG_FB_CLPS711X=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_PLATFORM=y CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set # CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS=y
...@@ -77,6 +77,8 @@ CONFIG_LEDS_GPIO=y ...@@ -77,6 +77,8 @@ CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_PWM=y
CONFIG_PWM_CLPS711X=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y
CONFIG_CRAMFS=y CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y CONFIG_MINIX_FS=y
......
...@@ -6,10 +6,15 @@ CONFIG_RD_LZMA=y ...@@ -6,10 +6,15 @@ CONFIG_RD_LZMA=y
CONFIG_ARCH_HISI=y CONFIG_ARCH_HISI=y
CONFIG_ARCH_HI3xxx=y CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_HIX5HD2=y CONFIG_ARCH_HIX5HD2=y
CONFIG_ARCH_HIP04=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=16
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_UNIX=y CONFIG_UNIX=y
CONFIG_INET=y CONFIG_INET=y
...@@ -21,6 +26,12 @@ CONFIG_BLK_DEV_SD=y ...@@ -21,6 +26,12 @@ CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_OF_PLATFORM=y
...@@ -56,3 +67,5 @@ CONFIG_PRINTK_TIME=y ...@@ -56,3 +67,5 @@ CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y CONFIG_LOCKUP_DETECTOR=y
CONFIG_VFP=y
CONFIG_VFPv3=y
...@@ -21,7 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y ...@@ -21,7 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set # CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXC=y CONFIG_ARCH_MXC=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MACH_SCB9328=y CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y CONFIG_MACH_APF9328=y
CONFIG_MACH_MX21ADS=y CONFIG_MACH_MX21ADS=y
...@@ -38,8 +37,6 @@ CONFIG_PREEMPT=y ...@@ -38,8 +37,6 @@ CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_PM_DEBUG=y CONFIG_PM_DEBUG=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_PACKET=y CONFIG_PACKET=y
...@@ -58,6 +55,7 @@ CONFIG_NETFILTER=y ...@@ -58,6 +55,7 @@ CONFIG_NETFILTER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
CONFIG_IMX_WEIM=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
...@@ -73,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y ...@@ -73,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT25=y
CONFIG_ATA=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_PATA_IMX=y CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_CS89x0=y CONFIG_CS89x0=y
...@@ -97,10 +95,8 @@ CONFIG_SERIAL_8250=m ...@@ -97,10 +95,8 @@ CONFIG_SERIAL_8250=m
CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_HW_RANDOM is not set # CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y CONFIG_SPI_IMX=y
CONFIG_SPI_SPIDEV=y CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
...@@ -127,10 +123,7 @@ CONFIG_VIDEO_CODA=y ...@@ -127,10 +123,7 @@ CONFIG_VIDEO_CODA=y
CONFIG_SOC_CAMERA_OV2640=y CONFIG_SOC_CAMERA_OV2640=y
CONFIG_FB=y CONFIG_FB=y
CONFIG_FB_IMX=y CONFIG_FB_IMX=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y CONFIG_LCD_L4F00242T03=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y CONFIG_LOGO=y
CONFIG_SOUND=y CONFIG_SOUND=y
......
...@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y ...@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y
CONFIG_MACH_PCM043=y CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y CONFIG_MACH_VPR200=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX50=y CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SL=y
...@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y ...@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT25=y
# CONFIG_SCSI_PROC_FS is not set # CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_SCAN_ASYNC=y
...@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y ...@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MXC_RNGA=y
# CONFIG_I2C_COMPAT is not set # CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set # CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_IMX=y CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y CONFIG_GPIO_MC9S08DZ60=y
...@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y ...@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y CONFIG_LCD_L4F00242T03=y
CONFIG_LCD_PLATFORM=y CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_GPIO=y
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
...@@ -206,6 +202,7 @@ CONFIG_LOGO=y ...@@ -206,6 +202,7 @@ CONFIG_LOGO=y
CONFIG_SOUND=y CONFIG_SOUND=y
CONFIG_SND=y CONFIG_SND=y
CONFIG_SND_SOC=y CONFIG_SND_SOC=y
CONFIG_SND_SOC_FSL_SAI=y
CONFIG_SND_IMX_SOC=y CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_EUKREA_TLV320=y
...@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y ...@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y CONFIG_USB_EHCI_MXC=y
...@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y ...@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC=y
...@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y ...@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y
CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_TVE=y
CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_LDB=y
CONFIG_DRM_IMX_IPUV3_CORE=y
CONFIG_DRM_IMX_IPUV3=y CONFIG_DRM_IMX_IPUV3=y
CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_IMX_HDMI=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
......
...@@ -28,6 +28,7 @@ CONFIG_ARCH_HIGHBANK=y ...@@ -28,6 +28,7 @@ CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HISI=y CONFIG_ARCH_HISI=y
CONFIG_ARCH_HI3xxx=y CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_HIX5HD2=y CONFIG_ARCH_HIX5HD2=y
CONFIG_ARCH_HIP04=y
CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MXC=y CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX51=y CONFIG_SOC_IMX51=y
......
CONFIG_SYSVIPC=y CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
CONFIG_AUDIT=y
CONFIG_NO_HZ=y CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16 CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_CGROUP=y
CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y CONFIG_EXPERT=y
CONFIG_SLAB=y CONFIG_SLAB=y
...@@ -32,19 +49,26 @@ CONFIG_SOC_OMAP5=y ...@@ -32,19 +49,26 @@ CONFIG_SOC_OMAP5=y
CONFIG_SOC_AM33XX=y CONFIG_SOC_AM33XX=y
CONFIG_SOC_AM43XX=y CONFIG_SOC_AM43XX=y
CONFIG_SOC_DRA7XX=y CONFIG_SOC_DRA7XX=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_THUMBEE=y CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y CONFIG_ARM_ERRATA_411920=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=2 CONFIG_NR_CPUS=2
CONFIG_CMA=y CONFIG_CMA=y
CONFIG_SECCOMP=y
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
CONFIG_KEXEC=y CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_GENERIC_CPUFREQ_CPU0=y
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE=y
CONFIG_BINFMT_MISC=y CONFIG_BINFMT_MISC=y
CONFIG_PM_DEBUG=y CONFIG_PM_DEBUG=y
...@@ -61,7 +85,7 @@ CONFIG_IP_PNP_DHCP=y ...@@ -61,7 +85,7 @@ CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y CONFIG_IP_PNP_RARP=y
# CONFIG_INET_LRO is not set # CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set CONFIG_IPV6=y
CONFIG_NETFILTER=y CONFIG_NETFILTER=y
CONFIG_CAN=m CONFIG_CAN=m
CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN=m
...@@ -75,9 +99,6 @@ CONFIG_BT_HCIBCM203X=m ...@@ -75,9 +99,6 @@ CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBPA10X=m
CONFIG_CFG80211=m CONFIG_CFG80211=m
CONFIG_MAC80211=m CONFIG_MAC80211=m
CONFIG_MAC80211_RC_PID=y
CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y CONFIG_DMA_CMA=y
...@@ -101,9 +122,9 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 ...@@ -101,9 +122,9 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SENSORS_TSL2550=m CONFIG_SENSORS_TSL2550=m
CONFIG_BMP085_I2C=m CONFIG_BMP085_I2C=m
CONFIG_SENSORS_LIS3_I2C=m CONFIG_SENSORS_LIS3_I2C=m
CONFIG_SRAM=y
CONFIG_SCSI=y CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_MD=y CONFIG_MD=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
...@@ -138,7 +159,9 @@ CONFIG_KEYBOARD_GPIO=y ...@@ -138,7 +159,9 @@ CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_MATRIX=m CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_TWL4030=y CONFIG_KEYBOARD_TWL4030=y
CONFIG_INPUT_TOUCHSCREEN=y CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_INPUT_MISC=y CONFIG_INPUT_MISC=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_INPUT_TWL4030_PWRBUTTON=y
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
...@@ -162,7 +185,13 @@ CONFIG_DEBUG_GPIO=y ...@@ -162,7 +185,13 @@ CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_TWL4030=y CONFIG_GPIO_TWL4030=y
CONFIG_W1=y CONFIG_W1=y
CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_BQ27x00=m
CONFIG_CHARGER_ISP1704=m
CONFIG_CHARGER_TWL4030=m
CONFIG_CHARGER_BQ2415X=m
CONFIG_CHARGER_BQ24190=m
CONFIG_CHARGER_BQ24735=m
CONFIG_POWER_RESET=y
CONFIG_POWER_AVS=y CONFIG_POWER_AVS=y
CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM75=m
CONFIG_THERMAL=y CONFIG_THERMAL=y
...@@ -183,8 +212,8 @@ CONFIG_MFD_TPS65217=y ...@@ -183,8 +212,8 @@ CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS65218=y
CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65910=y
CONFIG_TWL6040_CORE=y CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_PBIAS=y
CONFIG_REGULATOR_TI_ABB=y CONFIG_REGULATOR_TI_ABB=y
CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS6507X=y
...@@ -192,12 +221,12 @@ CONFIG_REGULATOR_TPS65217=y ...@@ -192,12 +221,12 @@ CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_PBIAS=y
CONFIG_FB=y CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y CONFIG_FB_TILEBLITTING=y
CONFIG_OMAP2_DSS=m CONFIG_OMAP2_DSS=m
CONFIG_OMAP5_DSS_HDMI=y
CONFIG_OMAP2_DSS_SDI=y CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y CONFIG_OMAP2_DSS_DSI=y
CONFIG_FB_OMAP2=m CONFIG_FB_OMAP2=m
...@@ -205,11 +234,25 @@ CONFIG_DISPLAY_ENCODER_TFP410=m ...@@ -205,11 +234,25 @@ CONFIG_DISPLAY_ENCODER_TFP410=m
CONFIG_DISPLAY_ENCODER_TPD12S015=m CONFIG_DISPLAY_ENCODER_TPD12S015=m
CONFIG_DISPLAY_CONNECTOR_DVI=m CONFIG_DISPLAY_CONNECTOR_DVI=m
CONFIG_DISPLAY_CONNECTOR_HDMI=m CONFIG_DISPLAY_CONNECTOR_HDMI=m
CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
CONFIG_DISPLAY_PANEL_DPI=m CONFIG_DISPLAY_PANEL_DPI=m
CONFIG_DISPLAY_PANEL_DSI_CM=m
CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=m
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_PANDORA=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y CONFIG_LOGO=y
CONFIG_SOUND=m CONFIG_SOUND=m
...@@ -221,8 +264,6 @@ CONFIG_SND_DEBUG=y ...@@ -221,8 +264,6 @@ CONFIG_SND_DEBUG=y
CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=m CONFIG_SND_SOC=m
CONFIG_SND_OMAP_SOC=m CONFIG_SND_OMAP_SOC=m
CONFIG_SND_AM33XX_SOC_EVM=m
CONFIG_SND_DAVINCI_SOC=m
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
...@@ -233,9 +274,6 @@ CONFIG_USB_WDM=y ...@@ -233,9 +274,6 @@ CONFIG_USB_WDM=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=m CONFIG_USB_DWC3=m
CONFIG_USB_TEST=y CONFIG_USB_TEST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_AM335X_PHY_USB=y CONFIG_AM335X_PHY_USB=y
CONFIG_USB_GADGET=y CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG=y
...@@ -243,7 +281,6 @@ CONFIG_USB_GADGET_DEBUG_FILES=y ...@@ -243,7 +281,6 @@ CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_ZERO=m CONFIG_USB_ZERO=m
CONFIG_MMC=y CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_SDIO_UART=y CONFIG_SDIO_UART=y
CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS=y
...@@ -267,15 +304,23 @@ CONFIG_TI_EDMA=y ...@@ -267,15 +304,23 @@ CONFIG_TI_EDMA=y
CONFIG_DMA_OMAP=y CONFIG_DMA_OMAP=y
CONFIG_EXTCON=y CONFIG_EXTCON=y
CONFIG_EXTCON_PALMAS=y CONFIG_EXTCON_PALMAS=y
CONFIG_PWM=y
CONFIG_PWM_TWL=y
CONFIG_PWM_TWL_LED=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set # CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
CONFIG_QUOTA=y CONFIG_QUOTA=y
CONFIG_QFMT_V2=y CONFIG_QFMT_V2=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_XATTR=y
......
...@@ -19,6 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y ...@@ -19,6 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91=y
CONFIG_SOC_SAM_V7=y CONFIG_SOC_SAM_V7=y
CONFIG_SOC_SAMA5D3=y CONFIG_SOC_SAMA5D3=y
CONFIG_SOC_SAMA5D4=y
CONFIG_MACH_SAMA5_DT=y CONFIG_MACH_SAMA5_DT=y
CONFIG_AEABI=y CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set # CONFIG_OABI_COMPAT is not set
......
...@@ -20,7 +20,12 @@ ...@@ -20,7 +20,12 @@
* to consider dynamic allocation. * to consider dynamic allocation.
*/ */
#define MAX_CPUS_PER_CLUSTER 4 #define MAX_CPUS_PER_CLUSTER 4
#ifdef CONFIG_MCPM_QUAD_CLUSTER
#define MAX_NR_CLUSTERS 4
#else
#define MAX_NR_CLUSTERS 2 #define MAX_NR_CLUSTERS 2
#endif
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
/*
* Broadcom BCM63xx low-level UART debug
*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_bcm63xx.h>
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
.endm
.macro senduart, rd, rx
/* word access do not work */
strb \rd, [\rx, #UART_FIFO_REG]
.endm
.macro waituart, rd, rx
1001: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXEMPTY)
beq 1001b
.endm
.macro busyuart, rd, rx
1002: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXTRESH)
beq 1002b
.endm
/*
* Copyright (C) 2014 Carlo Caione
* Carlo Caione <carlo@caione.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define MESON_AO_UART_WFIFO 0x0
#define MESON_AO_UART_STATUS 0xc
#define MESON_AO_UART_TX_FIFO_EMPTY (1 << 22)
#define MESON_AO_UART_TX_FIFO_FULL (1 << 21)
.macro addruart, rp, rv, tmp
ldr \rp, =(CONFIG_DEBUG_UART_PHYS) @ physical
ldr \rv, =(CONFIG_DEBUG_UART_VIRT) @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #MESON_AO_UART_WFIFO]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
beq 1002b
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_FULL
bne 1001b
.endm
...@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0 ...@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0
config HAVE_AT91_DBGU1 config HAVE_AT91_DBGU1
bool bool
config HAVE_AT91_DBGU2
bool
config AT91_USE_OLD_CLK config AT91_USE_OLD_CLK
bool bool
...@@ -47,6 +50,9 @@ config AT91_SAM9_TIME ...@@ -47,6 +50,9 @@ config AT91_SAM9_TIME
config HAVE_AT91_SMD config HAVE_AT91_SMD
bool bool
config HAVE_AT91_H32MX
bool
config SOC_AT91SAM9 config SOC_AT91SAM9
bool bool
select AT91_SAM9_TIME select AT91_SAM9_TIME
...@@ -105,6 +111,21 @@ config SOC_SAMA5D3 ...@@ -105,6 +111,21 @@ config SOC_SAMA5D3
help help
Select this if you are using one of Atmel's SAMA5D3 family SoC. Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config SOC_SAMA5D4
bool "SAMA5D4 family"
select SOC_SAMA5
select HAVE_AT91_DBGU2
select CLKSRC_MMIO
select CACHE_L2X0
select CACHE_PL310
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
help
Select this if you are using one of Atmel's SAMA5D4 family SoC.
endif endif
if SOC_SAM_V4_V5 if SOC_SAM_V4_V5
......
...@@ -24,6 +24,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o ...@@ -24,6 +24,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
......
...@@ -62,7 +62,7 @@ static void __init sama5_dt_device_init(void) ...@@ -62,7 +62,7 @@ static void __init sama5_dt_device_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
} }
static const char *sama5_dt_board_compat[] __initdata = { static const char *sama5_dt_board_compat[] __initconst = {
"atmel,sama5", "atmel,sama5",
NULL NULL
}; };
...@@ -75,3 +75,17 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") ...@@ -75,3 +75,17 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
.init_machine = sama5_dt_device_init, .init_machine = sama5_dt_device_init,
.dt_compat = sama5_dt_board_compat, .dt_compat = sama5_dt_board_compat,
MACHINE_END MACHINE_END
static const char *sama5_alt_dt_board_compat[] __initconst = {
"atmel,sama5d4",
NULL
};
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
.map_io = at91_alt_map_io,
.init_early = at91_dt_initialize,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_alt_dt_board_compat,
.l2c_aux_mask = ~0UL,
MACHINE_END
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
/* Map io */ /* Map io */
extern void __init at91_map_io(void); extern void __init at91_map_io(void);
extern void __init at91_alt_map_io(void);
extern void __init at91_init_sram(int bank, unsigned long base, extern void __init at91_init_sram(int bank, unsigned long base,
unsigned int length); unsigned int length);
......
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#define ARCH_ID_AT91M40807 0x14080745 #define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840 #define ARCH_ID_AT91R40008 0x44000840
#define ARCH_ID_SAMA5D3 0x8A5C07C0 #define ARCH_ID_SAMA5 0x8A5C07C0
#define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002 #define ARCH_EXID_AT91SAM9M10 0x00000002
...@@ -49,12 +49,19 @@ ...@@ -49,12 +49,19 @@
#define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004 #define ARCH_EXID_AT91SAM9X25 0x00000004
#define ARCH_EXID_SAMA5D3 0x00004300
#define ARCH_EXID_SAMA5D31 0x00444300 #define ARCH_EXID_SAMA5D31 0x00444300
#define ARCH_EXID_SAMA5D33 0x00414300 #define ARCH_EXID_SAMA5D33 0x00414300
#define ARCH_EXID_SAMA5D34 0x00414301 #define ARCH_EXID_SAMA5D34 0x00414301
#define ARCH_EXID_SAMA5D35 0x00584300 #define ARCH_EXID_SAMA5D35 0x00584300
#define ARCH_EXID_SAMA5D36 0x00004301 #define ARCH_EXID_SAMA5D36 0x00004301
#define ARCH_EXID_SAMA5D4 0x00000007
#define ARCH_EXID_SAMA5D41 0x00000001
#define ARCH_EXID_SAMA5D42 0x00000002
#define ARCH_EXID_SAMA5D43 0x00000003
#define ARCH_EXID_SAMA5D44 0x00000004
#define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000
...@@ -86,6 +93,9 @@ enum at91_soc_type { ...@@ -86,6 +93,9 @@ enum at91_soc_type {
/* SAMA5D3 */ /* SAMA5D3 */
AT91_SOC_SAMA5D3, AT91_SOC_SAMA5D3,
/* SAMA5D4 */
AT91_SOC_SAMA5D4,
/* Unknown type */ /* Unknown type */
AT91_SOC_UNKNOWN, AT91_SOC_UNKNOWN,
}; };
...@@ -108,6 +118,10 @@ enum at91_soc_subtype { ...@@ -108,6 +118,10 @@ enum at91_soc_subtype {
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
/* SAMA5D4 */
AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
AT91_SOC_SAMA5D44,
/* No subtype for this SoC */ /* No subtype for this SoC */
AT91_SOC_SUBTYPE_NONE, AT91_SOC_SUBTYPE_NONE,
...@@ -211,6 +225,12 @@ static inline int at91_soc_is_detected(void) ...@@ -211,6 +225,12 @@ static inline int at91_soc_is_detected(void)
#define cpu_is_sama5d3() (0) #define cpu_is_sama5d3() (0)
#endif #endif
#ifdef CONFIG_SOC_SAMA5D4
#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
#else
#define cpu_is_sama5d4() (0)
#endif
/* /*
* Since this is ARM, we will never run on any AVR32 CPU. But these * Since this is ARM, we will never run on any AVR32 CPU. But these
* definitions may reduce clutter in common drivers. * definitions may reduce clutter in common drivers.
......
...@@ -16,8 +16,11 @@ ...@@ -16,8 +16,11 @@
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0) #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
#define AT91_DBGU AT91_BASE_DBGU0 #define AT91_DBGU AT91_BASE_DBGU0
#else #elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
#define AT91_DBGU AT91_BASE_DBGU1 #define AT91_DBGU AT91_BASE_DBGU1
#else
/* On sama5d4, use USART3 as low level serial console */
#define AT91_DBGU SAMA5D4_BASE_USART3
#endif #endif
.macro addruart, rp, rv, tmp .macro addruart, rp, rv, tmp
......
...@@ -19,8 +19,10 @@ ...@@ -19,8 +19,10 @@
/* DBGU base */ /* DBGU base */
/* rm9200, 9260/9g20, 9261/9g10, 9rl */ /* rm9200, 9260/9g20, 9261/9g10, 9rl */
#define AT91_BASE_DBGU0 0xfffff200 #define AT91_BASE_DBGU0 0xfffff200
/* 9263, 9g45 */ /* 9263, 9g45, sama5d3 */
#define AT91_BASE_DBGU1 0xffffee00 #define AT91_BASE_DBGU1 0xffffee00
/* sama5d4 */
#define AT91_BASE_DBGU2 0xfc069000
#if defined(CONFIG_ARCH_AT91X40) #if defined(CONFIG_ARCH_AT91X40)
#include <mach/at91x40.h> #include <mach/at91x40.h>
...@@ -34,6 +36,7 @@ ...@@ -34,6 +36,7 @@
#include <mach/at91sam9x5.h> #include <mach/at91sam9x5.h>
#include <mach/at91sam9n12.h> #include <mach/at91sam9n12.h>
#include <mach/sama5d3.h> #include <mach/sama5d3.h>
#include <mach/sama5d4.h>
/* /*
* On all at91 except rm9200 and x40 have the System Controller starts * On all at91 except rm9200 and x40 have the System Controller starts
...@@ -47,8 +50,14 @@ ...@@ -47,8 +50,14 @@
* and map the same memory space * and map the same memory space
*/ */
#define AT91_BASE_SYS 0xffffc000 #define AT91_BASE_SYS 0xffffc000
#endif #endif
/*
* On sama5d4 there is no system controller, we map some needed peripherals
*/
#define AT91_ALT_BASE_SYS 0xfc069000
/* /*
* On all at91 have the Advanced Interrupt Controller starts at address * On all at91 have the Advanced Interrupt Controller starts at address
* 0xfffff000 and the Power Management Controller starts at 0xfffffc00 * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
...@@ -69,23 +78,35 @@ ...@@ -69,23 +78,35 @@
*/ */
#define AT91_IO_PHYS_BASE 0xFFF78000 #define AT91_IO_PHYS_BASE 0xFFF78000
#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) #define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
/*
* On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
* to 0xFB069000 .. 0xFB06F000. (24Kb)
*/
#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
#else #else
/* /*
* Identity mapping for the non MMU case. * Identity mapping for the non MMU case.
*/ */
#define AT91_IO_PHYS_BASE AT91_BASE_SYS #define AT91_IO_PHYS_BASE AT91_BASE_SYS
#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) #define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS)
#endif #endif
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
/* Convert a physical IO address to virtual IO address */ /* Convert a physical IO address to virtual IO address */
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
/* /*
* Virtual to Physical Address mapping for IO devices. * Virtual to Physical Address mapping for IO devices.
*/ */
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
/* Internal SRAM is mapped below the IO devices */ /* Internal SRAM is mapped below the IO devices */
#define AT91_SRAM_MAX SZ_1M #define AT91_SRAM_MAX SZ_1M
......
/*
* Chip-specific header file for the SAMA5D4 family
*
* Copyright (C) 2013 Atmel Corporation,
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Common definitions.
* Based on SAMA5D4 datasheet.
*
* Licensed under GPLv2 or later.
*/
#ifndef SAMA5D4_H
#define SAMA5D4_H
/*
* User Peripheral physical base addresses.
*/
#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
/* Some other peripherals */
#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
/*
* Internal Memory.
*/
#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
#endif
...@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = { ...@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
0, 0,
}; };
static const u32 uarts_sama5[] = { static const u32 uarts_sama5d3[] = {
AT91_BASE_DBGU1, AT91_BASE_DBGU1,
SAMA5D3_BASE_USART0, SAMA5D3_BASE_USART0,
SAMA5D3_BASE_USART1, SAMA5D3_BASE_USART1,
...@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = { ...@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = {
0, 0,
}; };
static const u32 uarts_sama5d4[] = {
AT91_BASE_DBGU2,
SAMA5D4_BASE_USART3,
0,
};
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{ {
u32 cidr, socid; u32 cidr, socid;
...@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) ...@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
case ARCH_ID_AT91SAM9X5: case ARCH_ID_AT91SAM9X5:
return uarts_sam9x5; return uarts_sam9x5;
case ARCH_ID_SAMA5D3: case ARCH_ID_SAMA5:
return uarts_sama5; cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
if (cidr & ARCH_EXID_SAMA5D3)
return uarts_sama5d3;
else if (cidr & ARCH_EXID_SAMA5D4)
return uarts_sama5d4;
break;
} }
/* at91sam9g10 */ /* at91sam9g10 */
...@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void) ...@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void)
const u32* usarts; const u32* usarts;
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
if (!usarts) if (!usarts)
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
if (!usarts)
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
if (!usarts) { if (!usarts) {
at91_uart = NULL; at91_uart = NULL;
return; return;
......
/*
* Chip-specific setup code for the SAMA5D4 family
*
* Copyright (C) 2013 Atmel Corporation,
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d4.h>
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
* Processor initialization
* -------------------------------------------------------------------- */
static struct map_desc at91_io_desc[] __initdata = {
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
.length = SZ_512,
.type = MT_DEVICE,
},
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
.length = SZ_512,
.type = MT_DEVICE,
},
{ /* On sama5d4, we use USART3 as serial console */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
.length = SZ_256,
.type = MT_DEVICE,
},
{ /* A bunch of peripheral with fine grained IO space */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
.length = SZ_2K,
.type = MT_DEVICE,
},
};
static void __init sama5d4_map_io(void)
{
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
}
AT91_SOC_START(sama5d4)
.map_io = sama5d4_map_io,
AT91_SOC_END
...@@ -97,6 +97,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = { ...@@ -97,6 +97,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = {
.type = MT_DEVICE, .type = MT_DEVICE,
}; };
static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
.virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
.length = 24 * SZ_1K,
.type = MT_DEVICE,
};
static void __init soc_detect(u32 dbgu_base) static void __init soc_detect(u32 dbgu_base)
{ {
u32 cidr, socid; u32 cidr, socid;
...@@ -159,9 +166,12 @@ static void __init soc_detect(u32 dbgu_base) ...@@ -159,9 +166,12 @@ static void __init soc_detect(u32 dbgu_base)
at91_boot_soc = at91sam9n12_soc; at91_boot_soc = at91sam9n12_soc;
break; break;
case ARCH_ID_SAMA5D3: case ARCH_ID_SAMA5:
at91_soc_initdata.type = AT91_SOC_SAMA5D3; at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
at91_boot_soc = sama5d3_soc; if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
at91_boot_soc = sama5d3_soc;
}
break; break;
} }
...@@ -184,7 +194,8 @@ static void __init soc_detect(u32 dbgu_base) ...@@ -184,7 +194,8 @@ static void __init soc_detect(u32 dbgu_base)
at91_soc_initdata.cidr = cidr; at91_soc_initdata.cidr = cidr;
/* sub version of soc */ /* sub version of soc */
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); if (!at91_soc_initdata.exid)
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
switch (at91_soc_initdata.exid) { switch (at91_soc_initdata.exid) {
...@@ -241,6 +252,54 @@ static void __init soc_detect(u32 dbgu_base) ...@@ -241,6 +252,54 @@ static void __init soc_detect(u32 dbgu_base)
} }
} }
static void __init alt_soc_detect(u32 dbgu_base)
{
u32 cidr, socid;
/* SoC ID */
cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
socid = cidr & ~AT91_CIDR_VERSION;
switch (socid) {
case ARCH_ID_SAMA5:
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
at91_boot_soc = sama5d3_soc;
} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
at91_soc_initdata.type = AT91_SOC_SAMA5D4;
at91_boot_soc = sama5d4_soc;
}
break;
}
if (!at91_soc_is_detected())
return;
at91_soc_initdata.cidr = cidr;
/* sub version of soc */
if (!at91_soc_initdata.exid)
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
switch (at91_soc_initdata.exid) {
case ARCH_EXID_SAMA5D41:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
break;
case ARCH_EXID_SAMA5D42:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
break;
case ARCH_EXID_SAMA5D43:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
break;
case ARCH_EXID_SAMA5D44:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
break;
}
}
}
static const char *soc_name[] = { static const char *soc_name[] = {
[AT91_SOC_RM9200] = "at91rm9200", [AT91_SOC_RM9200] = "at91rm9200",
[AT91_SOC_SAM9260] = "at91sam9260", [AT91_SOC_SAM9260] = "at91sam9260",
...@@ -253,6 +312,7 @@ static const char *soc_name[] = { ...@@ -253,6 +312,7 @@ static const char *soc_name[] = {
[AT91_SOC_SAM9X5] = "at91sam9x5", [AT91_SOC_SAM9X5] = "at91sam9x5",
[AT91_SOC_SAM9N12] = "at91sam9n12", [AT91_SOC_SAM9N12] = "at91sam9n12",
[AT91_SOC_SAMA5D3] = "sama5d3", [AT91_SOC_SAMA5D3] = "sama5d3",
[AT91_SOC_SAMA5D4] = "sama5d4",
[AT91_SOC_UNKNOWN] = "Unknown", [AT91_SOC_UNKNOWN] = "Unknown",
}; };
...@@ -280,6 +340,10 @@ static const char *soc_subtype_name[] = { ...@@ -280,6 +340,10 @@ static const char *soc_subtype_name[] = {
[AT91_SOC_SAMA5D34] = "sama5d34", [AT91_SOC_SAMA5D34] = "sama5d34",
[AT91_SOC_SAMA5D35] = "sama5d35", [AT91_SOC_SAMA5D35] = "sama5d35",
[AT91_SOC_SAMA5D36] = "sama5d36", [AT91_SOC_SAMA5D36] = "sama5d36",
[AT91_SOC_SAMA5D41] = "sama5d41",
[AT91_SOC_SAMA5D42] = "sama5d42",
[AT91_SOC_SAMA5D43] = "sama5d43",
[AT91_SOC_SAMA5D44] = "sama5d44",
[AT91_SOC_SUBTYPE_NONE] = "None", [AT91_SOC_SUBTYPE_NONE] = "None",
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
}; };
...@@ -342,6 +406,31 @@ void __init at91_ioremap_rstc(u32 base_addr) ...@@ -342,6 +406,31 @@ void __init at91_ioremap_rstc(u32 base_addr)
panic("Impossible to ioremap at91_rstc_base\n"); panic("Impossible to ioremap at91_rstc_base\n");
} }
void __init at91_alt_map_io(void)
{
/* Map peripherals */
iotable_init(&at91_alt_io_desc, 1);
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
alt_soc_detect(AT91_BASE_DBGU2);
if (!at91_soc_is_detected())
panic("AT91: Impossible to detect the SOC type");
pr_info("AT91: Detected soc type: %s\n",
at91_get_soc_type(&at91_soc_initdata));
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
pr_info("AT91: Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (!at91_soc_is_enabled())
panic("AT91: Soc not enabled");
if (at91_boot_soc.map_io)
at91_boot_soc.map_io();
}
void __iomem *at91_matrix_base; void __iomem *at91_matrix_base;
EXPORT_SYMBOL_GPL(at91_matrix_base); EXPORT_SYMBOL_GPL(at91_matrix_base);
......
...@@ -24,6 +24,7 @@ extern struct at91_init_soc at91sam9rl_soc; ...@@ -24,6 +24,7 @@ extern struct at91_init_soc at91sam9rl_soc;
extern struct at91_init_soc at91sam9x5_soc; extern struct at91_init_soc at91sam9x5_soc;
extern struct at91_init_soc at91sam9n12_soc; extern struct at91_init_soc at91sam9n12_soc;
extern struct at91_init_soc sama5d3_soc; extern struct at91_init_soc sama5d3_soc;
extern struct at91_init_soc sama5d4_soc;
#define AT91_SOC_START(_name) \ #define AT91_SOC_START(_name) \
struct at91_init_soc __initdata _name##_soc \ struct at91_init_soc __initdata _name##_soc \
...@@ -74,3 +75,7 @@ static inline int at91_soc_is_enabled(void) ...@@ -74,3 +75,7 @@ static inline int at91_soc_is_enabled(void)
#if !defined(CONFIG_SOC_SAMA5D3) #if !defined(CONFIG_SOC_SAMA5D3)
#define sama5d3_soc at91_boot_soc #define sama5d3_soc at91_boot_soc
#endif #endif
#if !defined(CONFIG_SOC_SAMA5D4)
#define sama5d4_soc at91_boot_soc
#endif
...@@ -99,6 +99,23 @@ config ARCH_BCM_5301X ...@@ -99,6 +99,23 @@ config ARCH_BCM_5301X
different SoC or with the older BCM47XX and BCM53XX based different SoC or with the older BCM47XX and BCM53XX based
network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
config ARCH_BCM_63XX
bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
depends on MMU
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_TWD if SMP
select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
This enables support for systems based on Broadcom DSL SoCs.
It currently supports the 'BCM63XX' ARM-based family, which includes
the BCM63138 variant.
config ARCH_BRCMSTB config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7 bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
depends on MMU depends on MMU
......
...@@ -34,6 +34,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o ...@@ -34,6 +34,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
# BCM5301X # BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
# BCM63XXx
obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y) ifeq ($(CONFIG_ARCH_BRCMSTB),y)
obj-y += brcmstb.o obj-y += brcmstb.o
endif endif
/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
static const char * const bcm63xx_dt_compat[] = {
"brcm,bcm63138",
NULL
};
DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
.dt_compat = bcm63xx_dt_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END
...@@ -14,8 +14,9 @@ ...@@ -14,8 +14,9 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/i2c-gpio.h> #include <linux/i2c-gpio.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/backlight.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/memblock.h> #include <linux/memblock.h>
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
...@@ -108,23 +109,23 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = { ...@@ -108,23 +109,23 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
.set_power = edb7211_lcd_power_set, .set_power = edb7211_lcd_power_set,
}; };
static void edb7211_lcd_backlight_set_intensity(int intensity) static struct pwm_lookup edb7211_pwm_lookup[] = {
{ PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
gpio_set_value(EDB7211_LCDBL, !!intensity); 0, PWM_POLARITY_NORMAL),
clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON); };
}
static struct generic_bl_info edb7211_lcd_backlight_pdata = { static struct platform_pwm_backlight_data pwm_bl_pdata = {
.name = "lcd-backlight.0", .dft_brightness = 0x01,
.default_intensity = 0x01, .max_brightness = 0x0f,
.max_intensity = 0x0f, .enable_gpio = EDB7211_LCDBL,
.set_bl_intensity = edb7211_lcd_backlight_set_intensity,
}; };
static struct resource clps711x_pwm_res =
DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
static struct gpio edb7211_gpios[] __initconst = { static struct gpio edb7211_gpios[] __initconst = {
{ EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" }, { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
{ EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" }, { EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
{ EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" },
}; };
/* Reserve screen memory region at the start of main system memory. */ /* Reserve screen memory region at the start of main system memory. */
...@@ -153,12 +154,18 @@ static void __init edb7211_init_late(void) ...@@ -153,12 +154,18 @@ static void __init edb7211_init_late(void)
gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
platform_device_register(&edb7211_flash_pdev); platform_device_register(&edb7211_flash_pdev);
platform_device_register_data(NULL, "platform-lcd", 0, platform_device_register_data(NULL, "platform-lcd", 0,
&edb7211_lcd_power_pdata, &edb7211_lcd_power_pdata,
sizeof(edb7211_lcd_power_pdata)); sizeof(edb7211_lcd_power_pdata));
platform_device_register_data(NULL, "generic-bl", 0,
&edb7211_lcd_backlight_pdata, platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
sizeof(edb7211_lcd_backlight_pdata)); &clps711x_pwm_res, 1);
pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
platform_device_register_data(&platform_bus, "pwm-backlight", 0,
&pwm_bl_pdata, sizeof(pwm_bl_pdata));
platform_device_register_simple("video-clps711x", 0, NULL, 0); platform_device_register_simple("video-clps711x", 0, NULL, 0);
platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource, platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
ARRAY_SIZE(edb7211_cs8900_resource)); ARRAY_SIZE(edb7211_cs8900_resource));
......
/* /*
* CLPS711X common devices definitions * CLPS711X common devices definitions
* *
* Author: Alexander Shiyan <shc_work@mail.ru>, 2013 * Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
...@@ -9,8 +9,15 @@ ...@@ -9,8 +9,15 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#include <linux/io.h>
#include <linux/of_fdt.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/random.h>
#include <linux/sizes.h> #include <linux/sizes.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <asm/system_info.h>
#include <mach/hardware.h> #include <mach/hardware.h>
...@@ -90,10 +97,53 @@ static void __init clps711x_add_uart(void) ...@@ -90,10 +97,53 @@ static void __init clps711x_add_uart(void)
ARRAY_SIZE(clps711x_uart2_res)); ARRAY_SIZE(clps711x_uart2_res));
}; };
static void __init clps711x_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
void __iomem *base;
u32 id[5];
base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
if (!base)
return;
id[0] = readl(base + UNIQID);
id[1] = readl(base + RANDID0);
id[2] = readl(base + RANDID1);
id[3] = readl(base + RANDID2);
id[4] = readl(base + RANDID3);
system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
add_device_randomness(id, sizeof(id));
system_serial_low = id[0];
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
goto out_unmap;
soc_dev_attr->machine = of_flat_dt_get_machine_name();
soc_dev_attr->family = "Cirrus Logic CLPS711X";
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr->soc_id);
kfree(soc_dev_attr);
}
out_unmap:
iounmap(base);
}
void __init clps711x_devices_init(void) void __init clps711x_devices_init(void)
{ {
clps711x_add_cpuidle(); clps711x_add_cpuidle();
clps711x_add_gpio(); clps711x_add_gpio();
clps711x_add_syscon(); clps711x_add_syscon();
clps711x_add_uart(); clps711x_add_uart();
clps711x_soc_init();
} }
config ARCH_HISI config ARCH_HISI
bool "Hisilicon SoC Support" bool "Hisilicon SoC Support"
depends on ARCH_MULTIPLATFORM depends on ARCH_MULTI_V7
select ARM_AMBA select ARM_AMBA
select ARM_GIC select ARM_GIC
select ARM_TIMER_SP804 select ARM_TIMER_SP804
...@@ -22,6 +22,15 @@ config ARCH_HI3xxx ...@@ -22,6 +22,15 @@ config ARCH_HI3xxx
help help
Support for Hisilicon Hi36xx SoC family Support for Hisilicon Hi36xx SoC family
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select MCPM if SMP
select MCPM_QUAD_CLUSTER if SMP
help
Support for Hisilicon HiP04 SoC family
config ARCH_HIX5HD2 config ARCH_HIX5HD2
bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7 bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
select CACHE_L2X0 select CACHE_L2X0
......
...@@ -2,5 +2,8 @@ ...@@ -2,5 +2,8 @@
# Makefile for Hisilicon processors family # Makefile for Hisilicon processors family
# #
CFLAGS_platmcpm.o := -march=armv7-a
obj-y += hisilicon.o obj-y += hisilicon.o
obj-$(CONFIG_MCPM) += platmcpm.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
...@@ -63,3 +63,12 @@ static const char *hix5hd2_compat[] __initconst = { ...@@ -63,3 +63,12 @@ static const char *hix5hd2_compat[] __initconst = {
DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)") DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
.dt_compat = hix5hd2_compat, .dt_compat = hix5hd2_compat,
MACHINE_END MACHINE_END
static const char *hip04_compat[] __initconst = {
"hisilicon,hip04-d01",
NULL,
};
DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.dt_compat = hip04_compat,
MACHINE_END
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...@@ -69,6 +69,7 @@ config SOC_IMX1 ...@@ -69,6 +69,7 @@ config SOC_IMX1
select CPU_ARM920T select CPU_ARM920T
select IMX_HAVE_IOMUX_V1 select IMX_HAVE_IOMUX_V1
select MXC_AVIC select MXC_AVIC
select PINCTRL_IMX1
config SOC_IMX21 config SOC_IMX21
bool bool
...@@ -124,6 +125,13 @@ config MACH_APF9328 ...@@ -124,6 +125,13 @@ config MACH_APF9328
help help
Say Yes here if you are using the Armadeus APF9328 development board Say Yes here if you are using the Armadeus APF9328 development board
config MACH_IMX1_DT
bool "Support i.MX1 platforms from device tree"
select SOC_IMX1
help
Include support for Freescale i.MX1 based platforms
using the device tree for discovery.
endif endif
if ARCH_MULTI_V5 if ARCH_MULTI_V5
......
...@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y) ...@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
clk-pfd.o clk-busy.o clk.o \ clk-pfd.o clk-busy.o clk.o \
clk-fixup-div.o clk-fixup-mux.o clk-fixup-div.o clk-fixup-mux.o \
clk-gate-exclusive.o
obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
...@@ -43,6 +44,7 @@ endif ...@@ -43,6 +44,7 @@ endif
# i.MX1 based machines # i.MX1 based machines
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
# i.MX21 based machines # i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
......
...@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void) ...@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void)
case 2: case 2:
revision = IMX_CHIP_REVISION_1_2; revision = IMX_CHIP_REVISION_1_2;
break; break;
case 3:
revision = IMX_CHIP_REVISION_1_3;
break;
case 4:
revision = IMX_CHIP_REVISION_1_4;
break;
case 5:
/*
* i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
* as 'D' in Part Number last character.
*/
revision = IMX_CHIP_REVISION_1_5;
break;
default: default:
revision = IMX_CHIP_REVISION_UNKNOWN; revision = IMX_CHIP_REVISION_UNKNOWN;
} }
......
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include "clk.h"
/**
* struct clk_gate_exclusive - i.MX specific gate clock which is mutually
* exclusive with other gate clocks
*
* @gate: the parent class
* @exclusive_mask: mask of gate bits which are mutually exclusive to this
* gate clock
*
* The imx exclusive gate clock is a subclass of basic clk_gate
* with an addtional mask to indicate which other gate bits in the same
* register is mutually exclusive to this gate clock.
*/
struct clk_gate_exclusive {
struct clk_gate gate;
u32 exclusive_mask;
};
static int clk_gate_exclusive_enable(struct clk_hw *hw)
{
struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
struct clk_gate_exclusive *exgate = container_of(gate,
struct clk_gate_exclusive, gate);
u32 val = readl(gate->reg);
if (val & exgate->exclusive_mask)
return -EBUSY;
return clk_gate_ops.enable(hw);
}
static void clk_gate_exclusive_disable(struct clk_hw *hw)
{
clk_gate_ops.disable(hw);
}
static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
{
return clk_gate_ops.is_enabled(hw);
}
static const struct clk_ops clk_gate_exclusive_ops = {
.enable = clk_gate_exclusive_enable,
.disable = clk_gate_exclusive_disable,
.is_enabled = clk_gate_exclusive_is_enabled,
};
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask)
{
struct clk_gate_exclusive *exgate;
struct clk_gate *gate;
struct clk *clk;
struct clk_init_data init;
if (exclusive_mask == 0)
return ERR_PTR(-EINVAL);
exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
if (!exgate)
return ERR_PTR(-ENOMEM);
gate = &exgate->gate;
init.name = name;
init.ops = &clk_gate_exclusive_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent ? &parent : NULL;
init.num_parents = parent ? 1 : 0;
gate->reg = reg;
gate->bit_idx = shift;
gate->lock = &imx_ccm_lock;
gate->hw.init = &init;
exgate->exclusive_mask = exclusive_mask;
clk = clk_register(NULL, &gate->hw);
if (IS_ERR(clk))
kfree(exgate);
return clk;
}
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