- Don't show clk phase when it is invalid

* clk-phase-errors:
  clk: rockchip: fix mmc get phase
  clk: Fix phase init check
  clk: Bail out when calculating phase fails during clk registration
  clk: Move rate and accuracy recalc to mostly consumer APIs
  clk: Use 'parent' to shorten lines in __clk_core_init()
  clk: Don't cache errors from clk_ops::get_phase()

* clk-amlogic:
  clk: meson: meson8b: set audio output clock hierarchy
  clk: meson: g12a: add support for the SPICC SCLK Source clocks
  dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
  clk: meson: gxbb: set audio output clock hierarchy
  clk: meson: gxbb: add the gxl internal dac gate
  dt-bindings: clk: meson: add the gxl internal dac gate

* clk-renesas:
  dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
  clk: renesas: rcar-usb2-clock-sel: Add reset_control
  clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
  clk: renesas: Remove use of ARCH_R8A7795
  clk: renesas: r8a77965: Add RPC clocks
  clk: renesas: r8a7796: Add RPC clocks
  clk: renesas: r8a7795: Add RPC clocks
  clk: renesas: rcar-gen3: Add CCREE clocks

* clk-allwinner:
  clk: sunxi-ng: sun8i-de2: Sort structures
  clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
  clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
  clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
  clk: sunxi-ng: sun8i-de2: Split out H5 definitions
  clk: sunxi-ng: a64: Export MBUS clock

* clk-samsung:
  clk: samsung: Remove redundant check in samsung_cmu_register_one

* clk-formatting:
  clk: Fix continuation of of_clk_detect_critical()

* clk-si5341:
  clk, clk-si5341: Support multiple input ports

* clk-socfpga:
  clk: socfpga: stratix10: simplify parameter passing
  clk: stratix10: use do_div() for 64-bit calculation

Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Chen-Yu Tsai:

Changes consist mainly of cleanups for the display engine clock driver,
correcting clocks that don't exist. Also, the MBUS clock on the A64 is
exported for the device tree to consume.

* tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun8i-de2: Sort structures
  clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
  clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
  clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
  clk: sunxi-ng: sun8i-de2: Split out H5 definitions
  clk: sunxi-ng: a64: Export MBUS clock

Merge tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

  - Improved clock/reset handling for the R-Car USB2 Clock Selector
  - Conversion to json-schema of the Renesas CPG/MSSR DT bindings

* tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
  clk: renesas: rcar-usb2-clock-sel: Add reset_control
  clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties

Convert the Renesas Clock Pulse Generator / Module Standby and Software
Reset Device Tree binding documentation to json-schema.

Note that #reset-cells was incorrecty marked a required property for
RZ/A2 before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200303094848.23670-1-geert+renesas@glider.be

This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This hardware needs to enable clocks of both host and peripheral.
So, this patch adds multiple clocks management.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-4-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds missing required properties of power-domains and resets.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.

Fixes: 311accb6 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-3-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Since the hardware requires to enable both USB 2.0 host and peripheral
functional clock, this patch fixes the documentation.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.

Fixes: 311accb6 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-2-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Pull Amlogic clk driver updates from Jerome Brunet:

 - Update audio clock gate hierarchy for meson8 and gxbb
 - Update g12a spicc clock sources

* tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: set audio output clock hierarchy
  clk: meson: g12a: add support for the SPICC SCLK Source clocks
  dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
  clk: meson: gxbb: set audio output clock hierarchy
  clk: meson: gxbb: add the gxl internal dac gate
  dt-bindings: clk: meson: add the gxl internal dac gate

Merge tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3
  - Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N

* tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Remove use of ARCH_R8A7795
  clk: renesas: r8a77965: Add RPC clocks
  clk: renesas: r8a7796: Add RPC clocks
  clk: renesas: r8a7795: Add RPC clocks
  clk: renesas: rcar-gen3: Add CCREE clocks

If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.

Fixes: 27608786 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Commit 27608786 ("clk: Bail out when calculating phase fails during
clk registration") introduced a check on error values at the time the
clock is registered to bail out when such an error occurs. However, it
doesn't check whether the returned value is positive which will happen
if the driver returns a non-zero phase. Since a phase is usually a
non-zero positive number this ends up returning something that isn't 0
to the caller of __clk_core_init(), making most clks fail to register
if they implement a phase clk op and return anything besides 0 for the
phase.

Fix this by returning the error if phase is less than zero or just
return zero if the phase is a positive number.

Fixes: 27608786 ("clk: Bail out when calculating phase fails during clk registration")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lkml.kernel.org/r/20200225134248.919889-1-maxime@cerno.techReported-by: "kernelci.org bot" <bot@kernelci.org>
[sboyd@kernel.org: Reword commit text to provide clarity]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and
CONFIG_ARCH_R8A77951 in commit b925adfc ("soc: renesas: Add
ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200218112525.5834-1-geert+renesas@glider.be

The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the clock tree.

Fixes: e31a1900 ("meson: clk: Add support for clock gates")
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC
controller to provide a more complete range of frequencies instead of the
SPICC internal divider over Xtal.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the gxbb clock tree.

Fixes: 738f66d3 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Add the ACODEC clock gate to the gxl clk controller driver
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Add the gxl ACODEC clock id to the gxbb clock controller bindings
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Just pass the clock pointer structure to the various register functions.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-2-dinguyen@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-1-dinguyen@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The second line of the of_clk_detect_critical() function signature is
not indented according to coding style.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lkml.kernel.org/r/20191206133414.23925-1-geert+renesas@glider.beAcked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Consistent with other instances of samsung_clk_init, the check
if ctx is NULL is redundant. The function currently does not
return NULL.
Signed-off-by: Aditya Pakki <pakki001@umn.edu>
Link: https://lkml.kernel.org/r/20200121233349.28627-1-pakki001@umn.eduAcked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Bail out of clk registration if we fail to get the phase for a clk that
has a clk_ops::get_phase() callback. Print a warning too so that driver
authors can easily figure out that some clk is unable to read back phase
information at boot.

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-5-sboyd@kernel.orgAcked-by: Jerome Brunet <jbrunet@baylibre.com>

There's some confusion about when recalc is done for the rate and
accuracy clk consumer APIs in relation to the prepare lock being taken.
Oddly enough, we take the lock again in debugfs APIs so that we can call
the internal "clk_core" APIs to get these fields with any necessary
recalculations. Instead of having this confusion, let's introduce a
recalc variant of these two consumer APIs as internal helpers and call
them from the consumer APIs and the debugfs code so that we don't take
the lock more than once.

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-4-sboyd@kernel.orgAcked-by: Jerome Brunet <jbrunet@baylibre.com>

Some lines are getting long in this function. Let's move 'parent' up to
the top of the function and use it in many places whenever there is a
parent for a clk. This shortens some lines by avoiding core->parent->
indirections.

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-3-sboyd@kernel.orgAcked-by: Jerome Brunet <jbrunet@baylibre.com>

We don't check for errors from clk_ops::get_phase() before storing away
the result into the clk_core::phase member. This can lead to some fairly
confusing debugfs information if these ops do return an error. Let's
skip the store when this op fails to fix this. While we're here, move
the locking outside of clk_core_get_phase() to simplify callers from
the debugfs side.

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200205232802.29184-2-sboyd@kernel.orgAcked-by: Jerome Brunet <jbrunet@baylibre.com>

V3s quirks are not in right place. Move it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

R40 is actually very similar to A64, but it doesn't have mixer1 reset.
This means it's clocks and resets combination is unique and R40 specific
quirks are needed.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

A83T structures don't have clocks and reset for rotation core. Add them.

Fixes: 763c5bd0 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Currently, V3s and H3 reuse A83T reset structure. However, A83T contains
additional core for rotation, which is not present in V3s and H3.

Make new reset structure for H3 and let V3s reuse it. A83T reset
structure will be amended in subsequent commit.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

DE3 documentation regarding presence of rotate core in H6 is a bit
confusing. Register descriptions mention bits for enabling rotate core
clocks and reset, but general overview doesn't list it as feature of H6
display engine, BSP kernel doesn't support it and there is no interrupt
listed for it. Manual poking registers also didn't reveal presence of
rotate core.

Let's assume there isn't any rotate core on H6 present and remove
related clocks. With that done, structures are same as those for H5, so
just reuse H5 structure.

Fixes: 56808da9 ("clk: sunxi-ng: Add support for H6 DE3 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

A64 has rotation core which needs clocks and reset. Because there is no
appropriate structures available, make a separate, A64 specific
structures.

Fixes: cf4881c1 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

H5 has less clocks and resets than A64. Currently that's not obvious
because A64 is missing rotation core related clocks and reset.

Split out H5 definition. A64 structures will be fixed in subsequent
commit.

Note that this patch depends on commit 19368d99 ("clk: sunxi-ng:
add support for Allwinner H3 DE2 CCU") for the H3 clock list.

Fixes: 763c5bd0 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

MBUS clock will be referenced in MBUS controller node.

Export it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car M3-N (R8A77965)
CPG/MSSR driver.

Inspired by commit 94e3935b ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-3-dirk.behme@de.bosch.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car M3-W/M3-W+
(R8A7796) CPG/MSSR driver.

Inspired by commit 94e3935b ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-2-dirk.behme@de.bosch.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car H3 (R8A7795)
CPG/MSSR driver.

Inspired by commit 94e3935b ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-1-dirk.behme@de.bosch.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>