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Commit 132535cd authored by Thomas Gambier's avatar Thomas Gambier 🚴🏼
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Run dos2unix (to remove the CRLF line terminators)

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MiniPCIexpressCard/MiniPciExpressCard.PrjPCBStructure
View file @ 132535cd
Record=TopLevelDocument|FileName=MiniPCIe.SchDoc
Record=TopLevelDocument|FileName=MiniPCIe.SchDoc
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Design Rule Check - MiniPCIe.drc
View file @ 132535cd
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
Date : 10/01/2019
Time : 18:50:27
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Violations Detected : 0
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
Date : 10/01/2019
Time : 18:50:27
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:00:00
\ No newline at end of file
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.EXTREP
View file @ 132535cd
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 10/01/2019 18:50:37
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GBL Bottom Layer
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GBS Bottom Solder
.GM13 Dimension
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 10/01/2019 18:50:37
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GBL Bottom Layer
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GBS Bottom Solder
.GM13 Dimension
------------------------------------------------------------------------------------------
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.GBS
View file @ 132535cd
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%ADD18C,0.150*%
%ADD19C,0.250*%
D10*
X49096Y34875D02*
D03*
X48596D02*
D03*
X47096D02*
D03*
X46596D02*
D03*
X45096D02*
D03*
X44596D02*
D03*
X44096D02*
D03*
X43596D02*
D03*
X43096D02*
D03*
X42596D02*
D03*
X41096D02*
D03*
X40596D02*
D03*
X40096D02*
D03*
X39596D02*
D03*
X39096D02*
D03*
X38596D02*
D03*
X38096D02*
D03*
X36596D02*
D03*
X36096D02*
D03*
X35596D02*
D03*
X35096D02*
D03*
X34596D02*
D03*
X34096D02*
D03*
X33596D02*
D03*
X33096D02*
D03*
X32596D02*
D03*
X32096D02*
D03*
X31596D02*
D03*
X48096D02*
D03*
X47596D02*
D03*
X42096D02*
D03*
X41596D02*
D03*
X46096D02*
D03*
X45596D02*
D03*
X37596D02*
D03*
X37096D02*
D03*
D11*
X29696Y38125D02*
D03*
X50996D02*
D03*
M02*
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/NC Drill/NC Drill Files.LDP
View file @ 132535cd
Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
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