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Commit 132535cd authored by Thomas Gambier's avatar Thomas Gambier 🚴🏼
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Run dos2unix (to remove the CRLF line terminators)

parent 265fcd23
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MiniPCIexpressCard/MiniPciExpressCard.PrjPCBStructure
View file @ 132535cd
Record=TopLevelDocument|FileName=MiniPCIe.SchDoc Record=TopLevelDocument|FileName=MiniPCIe.SchDoc
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Design Rule Check - MiniPCIe.drc
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Protel Design System Design Rule Check Protel Design System Design Rule Check
PCB File : V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc PCB File : V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
Date : 10/01/2019 Date : 10/01/2019
Time : 18:50:27 Time : 18:50:27
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All) Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All) Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All) Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia) Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon) Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon) Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon) Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon) Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All) Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All) Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All) Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0 Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1')) Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0 Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2')) Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0 Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0 Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) ) Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0 Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All) Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0 Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0 Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All) Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All) Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All) Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All) Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0 Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All) Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0 Rule Violations :0
Violations Detected : 0 Violations Detected : 0
Time Elapsed : 00:00:00 Time Elapsed : 00:00:00
\ No newline at end of file
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.EXTREP
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------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 10/01/2019 18:50:37 Gerber File Extension Report For: Gerber Files.GBR 10/01/2019 18:50:37
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
Layer Extension Layer Description Layer Extension Layer Description
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
.GTL Top Layer .GTL Top Layer
.GBL Bottom Layer .GBL Bottom Layer
.GTO Top Overlay .GTO Top Overlay
.GTP Top Paste .GTP Top Paste
.GTS Top Solder .GTS Top Solder
.GBS Bottom Solder .GBS Bottom Solder
.GM13 Dimension .GM13 Dimension
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.GBS
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%FSLAX43Y43*% %FSLAX43Y43*%
%MOMM*% %MOMM*%
G71* G71*
G01* G01*
G75* G75*
G04 Layer_Color=16711935* G04 Layer_Color=16711935*
%ADD10R,0.300X1.300*% %ADD10R,0.300X1.300*%
%ADD11R,1.800X2.200*% %ADD11R,1.800X2.200*%
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%ADD13C,0.800*% %ADD13C,0.800*%
%ADD14C,0.200*% %ADD14C,0.200*%
%ADD15C,5.000*% %ADD15C,5.000*%
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%ADD18C,0.150*% %ADD18C,0.150*%
%ADD19C,0.250*% %ADD19C,0.250*%
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%ADD24C,0.100*% %ADD24C,0.100*%
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%ADD27C,0.700*% %ADD27C,0.700*%
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X33196D02* X33196D02*
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D03* D03*
X47596D02* X47596D02*
D03* D03*
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D03* D03*
X49196D02* X49196D02*
D03* D03*
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D03* D03*
X51596D02* X51596D02*
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D03* D03*
X44396D02* X44396D02*
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X43596D02* X43596D02*
D03* D03*
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D03* D03*
X47800D02* X47800D02*
D03* D03*
X47000D02* X47000D02*
D03* D03*
X46200D02* X46200D02*
D03* D03*
X32600D02* X32600D02*
D03* D03*
X33400D02* X33400D02*
D03* D03*
X34200D02* X34200D02*
D03* D03*
X35000D02* X35000D02*
D03* D03*
X35800D02* X35800D02*
D03* D03*
X36600D02* X36600D02*
D03* D03*
X37400D02* X37400D02*
D03* D03*
X38200D02* X38200D02*
D03* D03*
X39000D02* X39000D02*
D03* D03*
X39800D02* X39800D02*
D03* D03*
X40600D02* X40600D02*
D03* D03*
X42200D02* X42200D02*
D03* D03*
X43000D02* X43000D02*
D03* D03*
X43800D02* X43800D02*
D03* D03*
X44600D02* X44600D02*
D03* D03*
X45400D02* X45400D02*
D03* D03*
D25* D25*
X28496Y73500D02* X28496Y73500D02*
D03* D03*
X52696D02* X52696D02*
D03* D03*
Y49300D02* Y49300D02*
D03* D03*
X28496D02* X28496D02*
D03* D03*
D26* D26*
X46850Y36900D02* X46850Y36900D02*
D03* D03*
X36350D02* X36350D02*
D03* D03*
X52600Y31400D02* X52600Y31400D02*
D03* D03*
X28100D02* X28100D02*
D03* D03*
X40600Y32900D02* X40600Y32900D02*
D03* D03*
X43600D02* X43600D02*
D03* D03*
X48100Y41900D02* X48100Y41900D02*
D03* D03*
X43100D02* X43100D02*
D03* D03*
X38100D02* X38100D02*
D03* D03*
X33100D02* X33100D02*
D03* D03*
X53600Y38900D02* X53600Y38900D02*
D03* D03*
X27600Y39400D02* X27600Y39400D02*
D03* D03*
Y41900D02* Y41900D02*
D03* D03*
X53600D02* X53600D02*
D03* D03*
X50600Y33400D02* X50600Y33400D02*
D03* D03*
X30100D02* X30100D02*
D03* D03*
X51100Y29400D02* X51100Y29400D02*
D03* D03*
X48100D02* X48100D02*
D03* D03*
X42600D02* X42600D02*
D03* D03*
X38600D02* X38600D02*
D03* D03*
X34850D02* X34850D02*
D03* D03*
X31850D02* X31850D02*
D03* D03*
X30600D02* X30600D02*
D03* D03*
X48200Y31800D02* X48200Y31800D02*
D03* D03*
X47400D02* X47400D02*
D03* D03*
X39100Y31208D02* X39100Y31208D02*
D03* D03*
D27* D27*
X41400Y52400D02* X41400Y52400D02*
D03* D03*
M02* M02*
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.GM13
View file @ 132535cd
%FSLAX43Y43*% %FSLAX43Y43*%
%MOMM*% %MOMM*%
G71* G71*
G01* G01*
G75* G75*
G04 Layer_Color=16711935* G04 Layer_Color=16711935*
%ADD10R,0.300X1.300*% %ADD10R,0.300X1.300*%
%ADD11R,1.800X2.200*% %ADD11R,1.800X2.200*%
%ADD12R,0.600X2.500*% %ADD12R,0.600X2.500*%
%ADD13C,0.800*% %ADD13C,0.800*%
%ADD14C,0.200*% %ADD14C,0.200*%
%ADD15C,5.000*% %ADD15C,5.000*%
%ADD16C,0.550*% %ADD16C,0.550*%
%ADD17C,0.600*% %ADD17C,0.600*%
%ADD18C,0.150*% %ADD18C,0.150*%
%ADD19C,0.250*% %ADD19C,0.250*%
%ADD20R,29.211X9.310*% %ADD20R,29.211X9.310*%
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%ADD22R,1.900X2.300*% %ADD22R,1.900X2.300*%
%ADD23R,0.700X2.600*% %ADD23R,0.700X2.600*%
%ADD24C,0.100*% %ADD24C,0.100*%
%ADD25C,5.100*% %ADD25C,5.100*%
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%ADD27C,0.700*% %ADD27C,0.700*%
%ADD28C,0.020*% %ADD28C,0.020*%
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X27746Y28600D02* X27746Y28600D02*
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X27193Y29361D01* X27193Y29361D01*
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X31599Y51900D02* X31599Y51900D02*
X31849Y51967D01* X31849Y51967D01*
X32032Y52150D01* X32032Y52150D01*
X32099Y52400D01* X32099Y52400D01*
X32033Y52650D01* X32033Y52650D01*
X31850Y52833D01* X31850Y52833D01*
X31600Y52900D01* X31600Y52900D01*
X49600Y52900D02* X49600Y52900D02*
X49350Y52833D01* X49350Y52833D01*
X49167Y52650D01* X49167Y52650D01*
X49100Y52400D01* X49100Y52400D01*
X49167Y52150D01* X49167Y52150D01*
X49350Y51967D01* X49350Y51967D01*
X49600Y51900D01* X49600Y51900D01*
X54246Y29400D02* X54246Y29400D02*
X53999Y29361D01* X53999Y29361D01*
X53776Y29247D01* X53776Y29247D01*
X53599Y29070D01* X53599Y29070D01*
X53485Y28847D01* X53485Y28847D01*
X53446Y28600D01* X53446Y28600D01*
X37546Y29400D02* X37546Y29400D02*
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X37393Y29870D01* X37393Y29870D01*
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X36499Y30161D01* X36499Y30161D01*
X36276Y30047D01* X36276Y30047D01*
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X35946Y29400D01* X35946Y29400D01*
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X26946D01* X26946D01*
X25596D02* X25596D02*
Y51900D01* Y51900D01*
X31599D01* X31599D01*
X25596Y52900D02* X25596Y52900D02*
X31600Y52900D01* X31600Y52900D01*
X25596Y52900D02* X25596Y52900D02*
Y76541D01* Y76541D01*
X55596D01* X55596D01*
Y52900D02* Y52900D02*
Y76541D01* Y76541D01*
X49600Y52900D02* X49600Y52900D02*
X55596D01* X55596D01*
X49600Y51900D02* X49600Y51900D02*
X55596D01* X55596D01*
Y29400D02* Y29400D02*
Y51900D01* Y51900D01*
X54246Y29400D02* X54246Y29400D02*
X55596D01* X55596D01*
X53446Y25400D02* X53446Y25400D02*
Y28600D01* Y28600D01*
X37546Y25400D02* X37546Y25400D02*
X53446D01* X53446D01*
X37546D02* X37546D02*
Y29400D01* Y29400D01*
X35946Y25400D02* X35946Y25400D02*
Y29400D01* Y29400D01*
X27746Y25400D02* X27746Y25400D02*
X35946D01* X35946D01*
X27746D02* X27746D02*
Y28600D01* Y28600D01*
M02* M02*
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/Gerber/Gerber Files.GTP
View file @ 132535cd
%FSLAX43Y43*% %FSLAX43Y43*%
%MOMM*% %MOMM*%
G71* G71*
G01* G01*
G75* G75*
G04 Layer_Color=8421504* G04 Layer_Color=8421504*
%ADD10R,0.300X1.300*% %ADD10R,0.300X1.300*%
%ADD11R,1.800X2.200*% %ADD11R,1.800X2.200*%
%ADD12R,0.600X2.500*% %ADD12R,0.600X2.500*%
%ADD13C,0.800*% %ADD13C,0.800*%
%ADD14C,0.200*% %ADD14C,0.200*%
%ADD15C,5.000*% %ADD15C,5.000*%
%ADD16C,0.550*% %ADD16C,0.550*%
%ADD17C,0.600*% %ADD17C,0.600*%
%ADD18C,0.150*% %ADD18C,0.150*%
%ADD19C,0.250*% %ADD19C,0.250*%
D10* D10*
X49096Y34875D02* X49096Y34875D02*
D03* D03*
X48596D02* X48596D02*
D03* D03*
X47096D02* X47096D02*
D03* D03*
X46596D02* X46596D02*
D03* D03*
X45096D02* X45096D02*
D03* D03*
X44596D02* X44596D02*
D03* D03*
X44096D02* X44096D02*
D03* D03*
X43596D02* X43596D02*
D03* D03*
X43096D02* X43096D02*
D03* D03*
X42596D02* X42596D02*
D03* D03*
X41096D02* X41096D02*
D03* D03*
X40596D02* X40596D02*
D03* D03*
X40096D02* X40096D02*
D03* D03*
X39596D02* X39596D02*
D03* D03*
X39096D02* X39096D02*
D03* D03*
X38596D02* X38596D02*
D03* D03*
X38096D02* X38096D02*
D03* D03*
X36596D02* X36596D02*
D03* D03*
X36096D02* X36096D02*
D03* D03*
X35596D02* X35596D02*
D03* D03*
X35096D02* X35096D02*
D03* D03*
X34596D02* X34596D02*
D03* D03*
X34096D02* X34096D02*
D03* D03*
X33596D02* X33596D02*
D03* D03*
X33096D02* X33096D02*
D03* D03*
X32596D02* X32596D02*
D03* D03*
X32096D02* X32096D02*
D03* D03*
X31596D02* X31596D02*
D03* D03*
X48096D02* X48096D02*
D03* D03*
X47596D02* X47596D02*
D03* D03*
X42096D02* X42096D02*
D03* D03*
X41596D02* X41596D02*
D03* D03*
X46096D02* X46096D02*
D03* D03*
X45596D02* X45596D02*
D03* D03*
X37596D02* X37596D02*
D03* D03*
X37096D02* X37096D02*
D03* D03*
D11* D11*
X29696Y38125D02* X29696Y38125D02*
D03* D03*
X50996D02* X50996D02*
D03* D03*
M02* M02*
MiniPCIexpressCard/Project Outputs for MiniPciExpressCard/NC Drill/NC Drill Files.LDP
View file @ 132535cd
Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\2018\MiniPCIexpress\hard\MiniPCIe.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
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