- 31 Jul, 2020 22 commits
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Jonathan Marek authored
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by:
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Jonathan Marek authored
This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by:
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Jonathan Marek authored
Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9 to work around dpu_hw_reset_ubwc being broken. Signed-off-by:
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Jonathan Marek authored
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by:
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Jonathan Marek authored
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
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Rob Clark authored
Small cleanup, lets not open-code bits/bitfields that are properly defined in the rnndb xml (and therefore have builders in the generated headers) Signed-off-by:
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Rob Clark authored
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by:
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Jonathan Marek authored
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by:
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Jonathan Marek authored
A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by:
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Eric Anholt authored
We don't expect to find vbif_nrt or regdma on sdm845, but were clogging up dmesg with errors about it. Signed-off-by:
Eric Anholt <eric@anholt.net> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Eric Anholt authored
Nothing was using the lengths of these ioremaps. Signed-off-by:
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Rob Clark authored
If split-lm is used (for ex, on sdm845), we can have multiple ping- pongs, but only a single phys encoder. We need to configure dithering on each of them. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by:
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Akhil P Oommen authored
On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, move the refcount-get on GX PD before we initialize the GMU. This ensures that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen during GPU wake up during a system resume. Reported-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Tested-by:
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Rajendra Nayak authored
On SDM845 and SC7180 DSI needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate() for devices without an OPP table, hence the change works fine on devices/platforms which only need to set a clock rate. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
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Rajendra Nayak authored
On some qualcomm platforms DPU needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by:
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Rob Clark authored
This can happen a lot when things go pear shaped. Lets not flood dmesg when this happens. Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
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Sharat Masetty authored
This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by:
Sharat Masetty <smasetty@codeaurora.org> Signed-off-by:
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Sharat Masetty authored
Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Akhil P Oommen authored
Adding an msm_gem_object object to the inactive_list before completing its initialization is a bad idea because shrinker may pick it up from the inactive_list. Fix this by making sure that the initialization is complete before moving the msm_obj object to the inactive list. This patch fixes the below error: [10027.553044] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000068 [10027.573305] Mem abort info: [10027.590160] ESR = 0x96000006 [10027.597905] EC = 0x25: DABT (current EL), IL = 32 bits [10027.614430] SET = 0, FnV = 0 [10027.624427] EA = 0, S1PTW = 0 [10027.632722] Data abort info: [10027.638039] ISV = 0, ISS = 0x00000006 [10027.647459] CM = 0, WnR = 0 [10027.654345] user pgtable: 4k pages, 39-bit VAs, pgdp=00000001e3a6a000 [10027.672681] [0000000000000068] pgd=0000000198c31003, pud=0000000198c31003, pmd=0000000000000000 [10027.693900] Internal error: Oops: 96000006 [#1] PREEMPT SMP [10027.738261] CPU: 3 PID: 214 Comm: kswapd0 Tainted: G S 5.4.40 #1 [10027.745766] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT) [10027.752472] pstate: 80c00009 (Nzcv daif +PAN +UAO) [10027.757409] pc : mutex_is_locked+0x14/0x2c [10027.761626] lr : msm_gem_shrinker_count+0x70/0xec [10027.766454] sp : ffffffc011323ad0 [10027.769867] x29: ffffffc011323ad0 x28: ffffffe677e4b878 [10027.775324] x27: 0000000000000cc0 x26: 0000000000000000 [10027.780783] x25: ffffff817114a708 x24: 0000000000000008 [10027.786242] x23: ffffff8023ab7170 x22: 0000000000000001 [10027.791701] x21: ffffff817114a080 x20: 0000000000000119 [10027.797160] x19: 0000000000000068 x18: 00000000000003bc [10027.802621] x17: 0000000004a34210 x16: 00000000000000c0 [10027.808083] x15: 0000000000000000 x14: 0000000000000000 [10027.813542] x13: ffffffe677e0a3c0 x12: 0000000000000000 [10027.819000] x11: 0000000000000000 x10: ffffff8174b94340 [10027.824461] x9 : 0000000000000000 x8 : 0000000000000000 [10027.829919] x7 : 00000000000001fc x6 : ffffffc011323c88 [10027.835373] x5 : 0000000000000001 x4 : ffffffc011323d80 [10027.840832] x3 : ffffffff0477b348 x2 : 0000000000000000 [10027.846290] x1 : ffffffc011323b68 x0 : 0000000000000068 [10027.851748] Call trace: [10027.854264] mutex_is_locked+0x14/0x2c [10027.858121] msm_gem_shrinker_count+0x70/0xec [10027.862603] shrink_slab+0xc0/0x4b4 [10027.866187] shrink_node+0x4a8/0x818 [10027.869860] kswapd+0x624/0x890 [10027.873097] kthread+0x11c/0x12c [10027.876424] ret_from_fork+0x10/0x18 [10027.880102] Code: f9000bf3 910003fd aa0003f3 d503201f (f9400268) [10027.886362] ---[ end trace df5849a1a3543251 ]--- [10027.891518] Kernel panic - not syncing: Fatal exception Signed-off-by:
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Kalyan Thota authored
This change enables dither block for primary interface in display. Enabled for 6bpc in the current version. Changes in v1: - Remove redundant error checks (Rob). Signed-off-by:
Douglas Anderson <dianders@chromium.org> Tested-by:
Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by:
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Rob Clark authored
If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. v2: explicity check for interconnect-names property Fixes: 08af4769 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Fixes: 00bb9243 ("drm/msm/gpu: add support for ocmem interconnect path") Signed-off-by:
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- 30 Jul, 2020 5 commits
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Kalyan Thota authored
Setup an RGB HW pipe as cursor which can be used on secondary interface. For SC7180 2 HW pipes are enumerated as cursors 1 - primary interface 2 - secondary interface Signed-off-by:
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Kalyan Thota authored
"The PM core always increments the runtime usage counter before calling the ->suspend() callback and decrements it after calling the ->resume() callback" DPU and DSI are managed as runtime devices. When suspend is triggered, PM core adds a refcount on all the devices and calls device suspend, since usage count is already incremented, runtime suspend was not getting called and it kept the clocks on which resulted in target not entering into XO shutdown. Add changes to force suspend on runtime devices during pm sleep. Changes in v1: - Remove unnecessary checks in the function _dpu_kms_disable_dpu (Rob Clark). Changes in v2: - Avoid using suspend_late to reset the usagecount as suspend_late might not be called during suspend call failures (Doug). Changes in v3: - Use force suspend instead of managing device usage_count via runtime put and get API's to trigger callbacks (Doug). Changes in v4: - Check the return values of pm_runtime_force_suspend and pm_runtime_force_resume API's and pass appropriately (Doug). Changes in v5: - With v4 patch, test cycle has uncovered issues in device resume. On bubs: cmd tx failures were seen as SW is sending panel off commands when the dsi resources are turned off. Upon suspend, DRM driver will issue a NULL composition to the dpu, followed by turning off all the HW blocks. v5 changes will serialize the NULL commit and resource unwinding by handling them under PM prepare and PM complete phases there by ensuring that clks are on when panel off commands are being processed. Changes in v6: - Use drm_mode_config_helper_suspend/resume() instead of legacy API drm_atomic_helper_suspend/resume() (Doug). Trigger runtime callbacks from the suspend/resume call to turn off the resources. Changes in v7: - Add "__maybe_unused" to the functions to avoid compilation failures. Cleanup unnecessary configs (Doug). Signed-off-by: -
Jonathan Marek authored
Check for errors instead of silently not using icc if the msm driver probes before the interconnect driver. Allow ENODATA for ocmem path, as it is optional and this error is returned when "gfx-mem" path is provided but not "ocmem". Because msm_gpu_cleanup assumes msm_gpu_init has been called, the icc path init needs to be after msm_gpu_init for the error path to work. Signed-off-by:
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Jonathan Marek authored
These never get set back to 0 when probing fails, so an attempt to probe again results in broken behavior. Fix the problem by setting thse to zero before they are used. Signed-off-by:
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Jonathan Marek authored
adreno_gpu_init calls pm_runtime_enable, so adreno_gpu_cleanup needs to call pm_runtime_disable. Signed-off-by:
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- 29 Jul, 2020 2 commits
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Dave Airlie authored
This is confusing, and from my reading of all the drivers only nouveau got this right. Just make the API act under driver control of it's own allocation failing, and don't call destroy, if the page table fails to create there is nothing to cleanup here. (I'm willing to believe I've missed something here, so please review deeply). Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200728041736.20689-1-airlied@gmail.com
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Dave Airlie authored
Just drop the argument from this. This does ask the question if this is the function vmwgfx should be using or should it be doing an evict all like the other drivers. Reviewed-by:
Zack Rusin <zackr@vmware.com> Signed-off-by:
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- 28 Jul, 2020 2 commits
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Dave Airlie authored
This was removed in f5a9a938 ("drm/ttm: remove TTM_MEMTYPE_FLAG_CMA") but the the declaration was left dangling. Reviewed-by:
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Dave Airlie authored
The return value just led to BUG_ON, I think if a driver wants to BUG_ON here it can do it itself. (don't BUG_ON). Reviewed-by:
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- 27 Jul, 2020 2 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.9-2020-07-24: amdgpu: - Misc sienna cichlid fixes - Final bits of swSMU cleanup - Misc display fixes - Misc VCN fixes - Eeprom i2c cleanup - Drop amd vrr_range debugfs in favor of core drm Signed-off-by:
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git://github.com/skeggsb/linuxDave Airlie authored
- Conversion of all push buffer emission to a new set of macros, with better safety, sanity-checking, debug ability, and the use of NVIDIA's class headers. The headers have been trimmed to just what we use as they're rather extensive, the full versions can be found on NVIDIA's github[1]. - Proper push buffer space management for EVO/NVD channels. - Fixes to firmware loading behaviour in odd situations (various combinations of missing/incompatible FW). - runpm reference leak fixes - crc compile fixes without debugfs - 2MiB system memory pages support on Pascal and newer - misc other cleanups Signed-off-by:
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- 24 Jul, 2020 7 commits
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Lyude Paul authored
Looks like I made the mistake of forgetting to check whether or not this would build without CONFIG_DEBUG_FS, as the Kbuild bot reported some issues building with tegra_defconfig: In file included from drivers/gpu/drm/nouveau/nouveau_display.c:47: ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_head_crc_late_register’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:47: error: parameter name omitted 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:54: warning: no return statement in function returning non-void [-Wreturn-type] 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_handle_vblank’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:57: warning: ‘return’ with a value, in function returning void [-Wreturn-type] 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:1: note: declared here 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_check’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:23: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:43: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:9: error: parameter name omitted 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:16: warning: no return statement in function returning non-void [-Wreturn-type] 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_stop_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:114:32: error: parameter name omitted 114 | nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_prepare_notifier_contexts’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:116:43: error: parameter name omitted 116 | nv50_crc_atomic_prepare_notifier_contexts(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_start_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:118:33: error: parameter name omitted 118 | nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_set’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:21: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:41: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_clr’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:122:21: error: parameter name omitted 122 | nv50_crc_atomic_clr(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/nouveau/nouveau_display.c: In function ‘nouveau_framebuffer_new’: drivers/gpu/drm/nouveau/nouveau_display.c:286:15: warning: variable ‘width’ set but not used [-Wunused-but-set-variable] 286 | unsigned int width, height, i; | ^~~~~ So, fix the inline function declarations we use in drm/drivers/gpu/drm/nouveau/dispnv50/crc.h when CONFIG_DEBUG_FS is enabled. Fixes: 12885ecb ("drm/nouveau/kms/nvd9-: Add CRC support") Reported-by:Lyude Paul <lyude@redhat.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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