sdhci.c 110 KB
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/*
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 *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
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 *
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 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
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 *
 * Thanks to the following companies for their support:
 *
 *     - JMicron (hardware and technical support)
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 */

#include <linux/delay.h>
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#include <linux/ktime.h>
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#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <linux/sizes.h>
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#include <linux/swiotlb.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/leds.h>

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#include <linux/mmc/mmc.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sdhci.h"

#define DRIVER_NAME "sdhci"

#define DBG(f, x...) \
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	pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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#define SDHCI_DUMP(f, x...) \
	pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)

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#define MAX_TUNING_LOOP 40

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static unsigned int debug_quirks = 0;
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static unsigned int debug_quirks2;
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static void sdhci_finish_data(struct sdhci_host *);

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static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
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void sdhci_dumpregs(struct sdhci_host *host)
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{
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	SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");

	SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
		   sdhci_readl(host, SDHCI_DMA_ADDRESS),
		   sdhci_readw(host, SDHCI_HOST_VERSION));
	SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
		   sdhci_readw(host, SDHCI_BLOCK_SIZE),
		   sdhci_readw(host, SDHCI_BLOCK_COUNT));
	SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
		   sdhci_readl(host, SDHCI_ARGUMENT),
		   sdhci_readw(host, SDHCI_TRANSFER_MODE));
	SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
		   sdhci_readl(host, SDHCI_PRESENT_STATE),
		   sdhci_readb(host, SDHCI_HOST_CONTROL));
	SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
		   sdhci_readb(host, SDHCI_POWER_CONTROL),
		   sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
	SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
		   sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
		   sdhci_readw(host, SDHCI_CLOCK_CONTROL));
	SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
		   sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
		   sdhci_readl(host, SDHCI_INT_STATUS));
	SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
		   sdhci_readl(host, SDHCI_INT_ENABLE),
		   sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
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	SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
		   sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
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		   sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
	SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
		   sdhci_readl(host, SDHCI_CAPABILITIES),
		   sdhci_readl(host, SDHCI_CAPABILITIES_1));
	SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
		   sdhci_readw(host, SDHCI_COMMAND),
		   sdhci_readl(host, SDHCI_MAX_CURRENT));
	SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
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		   sdhci_readl(host, SDHCI_RESPONSE),
		   sdhci_readl(host, SDHCI_RESPONSE + 4));
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	SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
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		   sdhci_readl(host, SDHCI_RESPONSE + 8),
		   sdhci_readl(host, SDHCI_RESPONSE + 12));
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	SDHCI_DUMP("Host ctl2: 0x%08x\n",
		   sdhci_readw(host, SDHCI_HOST_CONTROL2));
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	if (host->flags & SDHCI_USE_ADMA) {
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		if (host->flags & SDHCI_USE_64_BIT_DMA) {
			SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
				   sdhci_readl(host, SDHCI_ADMA_ERROR),
				   sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
				   sdhci_readl(host, SDHCI_ADMA_ADDRESS));
		} else {
			SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
				   sdhci_readl(host, SDHCI_ADMA_ERROR),
				   sdhci_readl(host, SDHCI_ADMA_ADDRESS));
		}
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	}
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	SDHCI_DUMP("============================================\n");
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}
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EXPORT_SYMBOL_GPL(sdhci_dumpregs);
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/*****************************************************************************\
 *                                                                           *
 * Low level functions                                                       *
 *                                                                           *
\*****************************************************************************/

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static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
{
	return cmd->data || cmd->flags & MMC_RSP_BUSY;
}

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static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
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	u32 present;
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	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
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	    !mmc_card_is_removable(host->mmc))
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		return;

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	if (enable) {
		present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
				      SDHCI_CARD_PRESENT;
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		host->ier |= present ? SDHCI_INT_CARD_REMOVE :
				       SDHCI_INT_CARD_INSERT;
	} else {
		host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
	}
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	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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}

static void sdhci_enable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, true);
}

static void sdhci_disable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, false);
}

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static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
{
	if (host->bus_on)
		return;
	host->bus_on = true;
	pm_runtime_get_noresume(host->mmc->parent);
}

static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
{
	if (!host->bus_on)
		return;
	host->bus_on = false;
	pm_runtime_put_noidle(host->mmc->parent);
}

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void sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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	ktime_t timeout;
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	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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	if (mask & SDHCI_RESET_ALL) {
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		host->clock = 0;
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		/* Reset-all turns off SD Bus Power */
		if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
			sdhci_runtime_pm_bus_off(host);
	}
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	/* Wait max 100 ms */
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	timeout = ktime_add_ms(ktime_get(), 100);
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	/* hw clears the bit when it's done */
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	while (1) {
		bool timedout = ktime_after(ktime_get(), timeout);

		if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
			break;
		if (timedout) {
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			pr_err("%s: Reset 0x%x never completed.\n",
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				mmc_hostname(host->mmc), (int)mask);
			sdhci_dumpregs(host);
			return;
		}
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		udelay(10);
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	}
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}
EXPORT_SYMBOL_GPL(sdhci_reset);

static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
{
	if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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		struct mmc_host *mmc = host->mmc;

		if (!mmc->ops->get_cd(mmc))
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			return;
	}
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	host->ops->reset(host, mask);
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	if (mask & SDHCI_RESET_ALL) {
		if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
			if (host->ops->enable_dma)
				host->ops->enable_dma(host);
		}

		/* Resetting the controller clears many */
		host->preset_enabled = false;
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	}
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}

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static void sdhci_set_default_irqs(struct sdhci_host *host)
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{
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	host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
		    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
		    SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
		    SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
		    SDHCI_INT_RESPONSE;

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	if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
	    host->tuning_mode == SDHCI_TUNING_MODE_3)
		host->ier |= SDHCI_INT_RETUNE;

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	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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}

static void sdhci_init(struct sdhci_host *host, int soft)
{
	struct mmc_host *mmc = host->mmc;

	if (soft)
		sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
	else
		sdhci_do_reset(host, SDHCI_RESET_ALL);

	sdhci_set_default_irqs(host);
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	host->cqe_on = false;

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	if (soft) {
		/* force clock reconfiguration */
		host->clock = 0;
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		mmc->ops->set_ios(mmc, &mmc->ios);
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	}
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}
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static void sdhci_reinit(struct sdhci_host *host)
{
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	sdhci_init(host, 0);
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	sdhci_enable_card_detection(host);
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}

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static void __sdhci_led_activate(struct sdhci_host *host)
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{
	u8 ctrl;

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	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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	ctrl |= SDHCI_CTRL_LED;
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	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}

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static void __sdhci_led_deactivate(struct sdhci_host *host)
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{
	u8 ctrl;

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	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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	ctrl &= ~SDHCI_CTRL_LED;
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	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}

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#if IS_REACHABLE(CONFIG_LEDS_CLASS)
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static void sdhci_led_control(struct led_classdev *led,
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			      enum led_brightness brightness)
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{
	struct sdhci_host *host = container_of(led, struct sdhci_host, led);
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);

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	if (host->runtime_suspended)
		goto out;

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	if (brightness == LED_OFF)
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		__sdhci_led_deactivate(host);
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	else
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		__sdhci_led_activate(host);
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out:
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	spin_unlock_irqrestore(&host->lock, flags);
}
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static int sdhci_led_register(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;

	snprintf(host->led_name, sizeof(host->led_name),
		 "%s::", mmc_hostname(mmc));

	host->led.name = host->led_name;
	host->led.brightness = LED_OFF;
	host->led.default_trigger = mmc_hostname(mmc);
	host->led.brightness_set = sdhci_led_control;

	return led_classdev_register(mmc_dev(mmc), &host->led);
}

static void sdhci_led_unregister(struct sdhci_host *host)
{
	led_classdev_unregister(&host->led);
}

static inline void sdhci_led_activate(struct sdhci_host *host)
{
}

static inline void sdhci_led_deactivate(struct sdhci_host *host)
{
}

#else

static inline int sdhci_led_register(struct sdhci_host *host)
{
	return 0;
}

static inline void sdhci_led_unregister(struct sdhci_host *host)
{
}

static inline void sdhci_led_activate(struct sdhci_host *host)
{
	__sdhci_led_activate(host);
}

static inline void sdhci_led_deactivate(struct sdhci_host *host)
{
	__sdhci_led_deactivate(host);
}

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#endif

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/*****************************************************************************\
 *                                                                           *
 * Core functions                                                            *
 *                                                                           *
\*****************************************************************************/

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static void sdhci_read_block_pio(struct sdhci_host *host)
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{
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	unsigned long flags;
	size_t blksize, len, chunk;
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	u32 uninitialized_var(scratch);
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	u8 *buf;
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	DBG("PIO reading\n");
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	blksize = host->data->blksz;
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	chunk = 0;
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	local_irq_save(flags);
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	while (blksize) {
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		BUG_ON(!sg_miter_next(&host->sg_miter));
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		len = min(host->sg_miter.length, blksize);
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		blksize -= len;
		host->sg_miter.consumed = len;
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		buf = host->sg_miter.addr;
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		while (len) {
			if (chunk == 0) {
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				scratch = sdhci_readl(host, SDHCI_BUFFER);
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				chunk = 4;
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			}
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			*buf = scratch & 0xFF;

			buf++;
			scratch >>= 8;
			chunk--;
			len--;
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		}
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	}
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	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
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}
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static void sdhci_write_block_pio(struct sdhci_host *host)
{
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	unsigned long flags;
	size_t blksize, len, chunk;
	u32 scratch;
	u8 *buf;
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	DBG("PIO writing\n");

	blksize = host->data->blksz;
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	chunk = 0;
	scratch = 0;
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	local_irq_save(flags);
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	while (blksize) {
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		BUG_ON(!sg_miter_next(&host->sg_miter));
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		len = min(host->sg_miter.length, blksize);

		blksize -= len;
		host->sg_miter.consumed = len;

		buf = host->sg_miter.addr;
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		while (len) {
			scratch |= (u32)*buf << (chunk * 8);

			buf++;
			chunk++;
			len--;

			if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
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				sdhci_writel(host, scratch, SDHCI_BUFFER);
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				chunk = 0;
				scratch = 0;
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			}
		}
	}
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	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
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}

static void sdhci_transfer_pio(struct sdhci_host *host)
{
	u32 mask;

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	if (host->blocks == 0)
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		return;

	if (host->data->flags & MMC_DATA_READ)
		mask = SDHCI_DATA_AVAILABLE;
	else
		mask = SDHCI_SPACE_AVAILABLE;

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	/*
	 * Some controllers (JMicron JMB38x) mess up the buffer bits
	 * for transfers < 4 bytes. As long as it is just one block,
	 * we can ignore the bits.
	 */
	if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
		(host->data->blocks == 1))
		mask = ~0;

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	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
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		if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
			udelay(100);

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		if (host->data->flags & MMC_DATA_READ)
			sdhci_read_block_pio(host);
		else
			sdhci_write_block_pio(host);
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		host->blocks--;
		if (host->blocks == 0)
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			break;
	}
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	DBG("PIO transfer complete.\n");
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}

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static int sdhci_pre_dma_transfer(struct sdhci_host *host,
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				  struct mmc_data *data, int cookie)
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{
	int sg_count;

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	/*
	 * If the data buffers are already mapped, return the previous
	 * dma_map_sg() result.
	 */
	if (data->host_cookie == COOKIE_PRE_MAPPED)
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		return data->sg_count;

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	/* Bounce write requests to the bounce buffer */
	if (host->bounce_buffer) {
		unsigned int length = data->blksz * data->blocks;

		if (length > host->bounce_buffer_size) {
			pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
			       mmc_hostname(host->mmc), length,
			       host->bounce_buffer_size);
			return -EIO;
		}
		if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
			/* Copy the data to the bounce buffer */
			sg_copy_to_buffer(data->sg, data->sg_len,
					  host->bounce_buffer,
					  length);
		}
		/* Switch ownership to the DMA */
		dma_sync_single_for_device(host->mmc->parent,
					   host->bounce_addr,
					   host->bounce_buffer_size,
					   mmc_get_dma_dir(data));
		/* Just a dummy value */
		sg_count = 1;
	} else {
		/* Just access the data directly from memory */
		sg_count = dma_map_sg(mmc_dev(host->mmc),
				      data->sg, data->sg_len,
				      mmc_get_dma_dir(data));
	}
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	if (sg_count == 0)
		return -ENOSPC;

	data->sg_count = sg_count;
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	data->host_cookie = cookie;
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	return sg_count;
}

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static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
{
	local_irq_save(*flags);
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	return kmap_atomic(sg_page(sg)) + sg->offset;
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}

static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
{
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	kunmap_atomic(buffer);
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	local_irq_restore(*flags);
}

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static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
				  dma_addr_t addr, int len, unsigned cmd)
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{
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	struct sdhci_adma2_64_desc *dma_desc = desc;
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	/* 32-bit and 64-bit descriptors have these members in same position */
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	dma_desc->cmd = cpu_to_le16(cmd);
	dma_desc->len = cpu_to_le16(len);
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	dma_desc->addr_lo = cpu_to_le32((u32)addr);

	if (host->flags & SDHCI_USE_64_BIT_DMA)
		dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
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}

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static void sdhci_adma_mark_end(void *desc)
{
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	struct sdhci_adma2_64_desc *dma_desc = desc;
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	/* 32-bit and 64-bit descriptors have 'cmd' in same position */
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	dma_desc->cmd |= cpu_to_le16(ADMA2_END);
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}

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static void sdhci_adma_table_pre(struct sdhci_host *host,
	struct mmc_data *data, int sg_count)
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{
	struct scatterlist *sg;
	unsigned long flags;
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	dma_addr_t addr, align_addr;
	void *desc, *align;
	char *buffer;
	int len, offset, i;
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	/*
	 * The spec does not specify endianness of descriptor table.
	 * We currently guess that it is LE.
	 */

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	host->sg_count = sg_count;
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	desc = host->adma_table;
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	align = host->align_buffer;

	align_addr = host->align_addr;

	for_each_sg(data->sg, sg, host->sg_count, i) {
		addr = sg_dma_address(sg);
		len = sg_dma_len(sg);

		/*
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		 * The SDHCI specification states that ADMA addresses must
		 * be 32-bit aligned. If they aren't, then we use a bounce
		 * buffer for the (up to three) bytes that screw up the
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		 * alignment.
		 */
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		offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
			 SDHCI_ADMA2_MASK;
617 618 619 620 621 622 623
		if (offset) {
			if (data->flags & MMC_DATA_WRITE) {
				buffer = sdhci_kmap_atomic(sg, &flags);
				memcpy(align, buffer, offset);
				sdhci_kunmap_atomic(buffer, &flags);
			}

624
			/* tran, valid */
625
			sdhci_adma_write_desc(host, desc, align_addr, offset,
626
					      ADMA2_TRAN_VALID);
627 628 629

			BUG_ON(offset > 65536);

630 631
			align += SDHCI_ADMA2_ALIGN;
			align_addr += SDHCI_ADMA2_ALIGN;
632

633
			desc += host->desc_sz;
634 635 636 637 638 639 640

			addr += offset;
			len -= offset;
		}

		BUG_ON(len > 65536);

641 642 643 644 645 646
		if (len) {
			/* tran, valid */
			sdhci_adma_write_desc(host, desc, addr, len,
					      ADMA2_TRAN_VALID);
			desc += host->desc_sz;
		}
647 648 649 650 651

		/*
		 * If this triggers then we have a calculation bug
		 * somewhere. :/
		 */
652
		WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
653 654
	}

655
	if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
656
		/* Mark the last descriptor as the terminating descriptor */
657
		if (desc != host->adma_table) {
658
			desc -= host->desc_sz;
659
			sdhci_adma_mark_end(desc);
660 661
		}
	} else {
662
		/* Add a terminating entry - nop, end, valid */
663
		sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
664
	}
665 666 667 668 669 670 671
}

static void sdhci_adma_table_post(struct sdhci_host *host,
	struct mmc_data *data)
{
	struct scatterlist *sg;
	int i, size;
672
	void *align;
673 674 675
	char *buffer;
	unsigned long flags;

676 677
	if (data->flags & MMC_DATA_READ) {
		bool has_unaligned = false;
678

679 680 681 682 683 684
		/* Do a quick scan of the SG list for any unaligned mappings */
		for_each_sg(data->sg, sg, host->sg_count, i)
			if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
				has_unaligned = true;
				break;
			}
685

686 687
		if (has_unaligned) {
			dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
688
					    data->sg_len, DMA_FROM_DEVICE);
689

690
			align = host->align_buffer;
691

692 693 694 695 696 697 698 699
			for_each_sg(data->sg, sg, host->sg_count, i) {
				if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
					size = SDHCI_ADMA2_ALIGN -
					       (sg_dma_address(sg) & SDHCI_ADMA2_MASK);

					buffer = sdhci_kmap_atomic(sg, &flags);
					memcpy(buffer, align, size);
					sdhci_kunmap_atomic(buffer, &flags);
700

701 702
					align += SDHCI_ADMA2_ALIGN;
				}
703 704 705 706 707
			}
		}
	}
}

708 709 710 711 712 713 714 715
static u32 sdhci_sdma_address(struct sdhci_host *host)
{
	if (host->bounce_buffer)
		return host->bounce_addr;
	else
		return sg_dma_address(host->data->sg);
}

716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
static unsigned int sdhci_target_timeout(struct sdhci_host *host,
					 struct mmc_command *cmd,
					 struct mmc_data *data)
{
	unsigned int target_timeout;

	/* timeout in us */
	if (!data) {
		target_timeout = cmd->busy_timeout * 1000;
	} else {
		target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
		if (host->clock && data->timeout_clks) {
			unsigned long long val;

			/*
			 * data->timeout_clks is in units of clock cycles.
			 * host->clock is in Hz.  target_timeout is in us.
			 * Hence, us = 1000000 * cycles / Hz.  Round up.
			 */
			val = 1000000ULL * data->timeout_clks;
			if (do_div(val, host->clock))
				target_timeout++;
			target_timeout += val;
		}
	}

	return target_timeout;
}

745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777
static void sdhci_calc_sw_timeout(struct sdhci_host *host,
				  struct mmc_command *cmd)
{
	struct mmc_data *data = cmd->data;
	struct mmc_host *mmc = host->mmc;
	struct mmc_ios *ios = &mmc->ios;
	unsigned char bus_width = 1 << ios->bus_width;
	unsigned int blksz;
	unsigned int freq;
	u64 target_timeout;
	u64 transfer_time;

	target_timeout = sdhci_target_timeout(host, cmd, data);
	target_timeout *= NSEC_PER_USEC;

	if (data) {
		blksz = data->blksz;
		freq = host->mmc->actual_clock ? : host->clock;
		transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
		do_div(transfer_time, freq);
		/* multiply by '2' to account for any unknowns */
		transfer_time = transfer_time * 2;
		/* calculate timeout for the entire data */
		host->data_timeout = data->blocks * target_timeout +
				     transfer_time;
	} else {
		host->data_timeout = target_timeout;
	}

	if (host->data_timeout)
		host->data_timeout += MMC_CMD_TRANSFER_TIME;
}

778 779
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
			     bool *too_big)
780
{
781
	u8 count;
782
	struct mmc_data *data = cmd->data;
783
	unsigned target_timeout, current_timeout;
784

785 786
	*too_big = true;

787 788 789 790 791 792
	/*
	 * If the host controller provides us with an incorrect timeout
	 * value, just skip the check and use 0xE.  The hardware may take
	 * longer to time out, but that's much better than having a too-short
	 * timeout value.
	 */
793
	if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
794
		return 0xE;
795

796
	/* Unspecified timeout, assume max */
797
	if (!data && !cmd->busy_timeout)
798
		return 0xE;
799

800
	/* timeout in us */
801
	target_timeout = sdhci_target_timeout(host, cmd, data);
802

803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822
	/*
	 * Figure out needed cycles.
	 * We do this in steps in order to fit inside a 32 bit int.
	 * The first step is the minimum timeout, which will have a
	 * minimum resolution of 6 bits:
	 * (1) 2^13*1000 > 2^22,
	 * (2) host->timeout_clk < 2^16
	 *     =>
	 *     (1) / (2) > 2^6
	 */
	count = 0;
	current_timeout = (1 << 13) * 1000 / host->timeout_clk;
	while (current_timeout < target_timeout) {
		count++;
		current_timeout <<= 1;
		if (count >= 0xF)
			break;
	}

	if (count >= 0xF) {
823 824 825
		if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
			DBG("Too large timeout 0x%x requested for CMD%d!\n",
			    count, cmd->opcode);
826
		count = 0xE;
827 828
	} else {
		*too_big = false;
829 830
	}

831 832 833
	return count;
}

834 835 836 837 838 839
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
{
	u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
	u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;

	if (host->flags & SDHCI_REQ_USE_DMA)
840
		host->ier = (host->ier & ~pio_irqs) | dma_irqs;
841
	else
842 843
		host->ier = (host->ier & ~dma_irqs) | pio_irqs;

844 845 846 847 848
	if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
		host->ier |= SDHCI_INT_AUTO_CMD_ERR;
	else
		host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;

849 850
	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
851 852
}

853 854 855 856 857 858 859 860 861 862
static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
{
	if (enable)
		host->ier |= SDHCI_INT_DATA_TIMEOUT;
	else
		host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}

863
static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
864 865
{
	u8 count;
866 867 868 869

	if (host->ops->set_timeout) {
		host->ops->set_timeout(host, cmd);
	} else {
870 871 872 873 874 875
		bool too_big = false;

		count = sdhci_calc_timeout(host, cmd, &too_big);

		if (too_big &&
		    host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
876
			sdhci_calc_sw_timeout(host, cmd);
877 878 879 880 881
			sdhci_set_data_timeout_irq(host, false);
		} else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
			sdhci_set_data_timeout_irq(host, true);
		}

882 883 884 885 886 887
		sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
	}
}

static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
{
888
	u8 ctrl;
889
	struct mmc_data *data = cmd->data;
890

891 892
	host->data_timeout = 0;

893
	if (sdhci_data_line_cmd(cmd))
894
		sdhci_set_timeout(host, cmd);
895 896

	if (!data)
897 898
		return;

899 900
	WARN_ON(host->data);

901 902 903 904 905 906 907
	/* Sanity checks */
	BUG_ON(data->blksz * data->blocks > 524288);
	BUG_ON(data->blksz > host->mmc->max_blk_size);
	BUG_ON(data->blocks > 65535);

	host->data = data;
	host->data_early = 0;
908
	host->data->bytes_xfered = 0;
909

910
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
911
		struct scatterlist *sg;
912
		unsigned int length_mask, offset_mask;
913
		int i;
914

915 916 917 918 919 920 921 922 923
		host->flags |= SDHCI_REQ_USE_DMA;

		/*
		 * FIXME: This doesn't account for merging when mapping the
		 * scatterlist.
		 *
		 * The assumption here being that alignment and lengths are
		 * the same after DMA mapping to device address space.
		 */
924
		length_mask = 0;
925
		offset_mask = 0;
926
		if (host->flags & SDHCI_USE_ADMA) {
927
			if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
928
				length_mask = 3;
929 930 931 932 933 934 935
				/*
				 * As we use up to 3 byte chunks to work
				 * around alignment problems, we need to
				 * check the offset as well.
				 */
				offset_mask = 3;
			}
936 937
		} else {
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
938
				length_mask = 3;
939 940
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
				offset_mask = 3;
941 942
		}

943
		if (unlikely(length_mask | offset_mask)) {
944
			for_each_sg(data->sg, sg, data->sg_len, i) {
945
				if (sg->length & length_mask) {
946
					DBG("Reverting to PIO because of transfer size (%d)\n",
947
					    sg->length);
948 949 950
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
951
				if (sg->offset & offset_mask) {
952
					DBG("Reverting to PIO because of bad alignment\n");
953 954 955 956 957 958 959
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
			}
		}
	}

960
	if (host->flags & SDHCI_REQ_USE_DMA) {
961
		int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977

		if (sg_cnt <= 0) {
			/*
			 * This only happens when someone fed
			 * us an invalid request.
			 */
			WARN_ON(1);
			host->flags &= ~SDHCI_REQ_USE_DMA;
		} else if (host->flags & SDHCI_USE_ADMA) {
			sdhci_adma_table_pre(host, data, sg_cnt);

			sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
			if (host->flags & SDHCI_USE_64_BIT_DMA)
				sdhci_writel(host,
					     (u64)host->adma_addr >> 32,
					     SDHCI_ADMA_ADDRESS_HI);
978
		} else {
979
			WARN_ON(sg_cnt != 1);
980 981
			sdhci_writel(host, sdhci_sdma_address(host),
				     SDHCI_DMA_ADDRESS);
982 983 984
		}
	}

985 986 987 988 989 990
	/*
	 * Always adjust the DMA selection as some controllers
	 * (e.g. JMicron) can't do PIO properly when the selection
	 * is ADMA.
	 */
	if (host->version >= SDHCI_SPEC_200) {
991
		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
992 993
		ctrl &= ~SDHCI_CTRL_DMA_MASK;
		if ((host->flags & SDHCI_REQ_USE_DMA) &&
994 995 996 997 998 999
			(host->flags & SDHCI_USE_ADMA)) {
			if (host->flags & SDHCI_USE_64_BIT_DMA)
				ctrl |= SDHCI_CTRL_ADMA64;
			else
				ctrl |= SDHCI_CTRL_ADMA32;
		} else {
1000
			ctrl |= SDHCI_CTRL_SDMA;
1001
		}
1002
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1003 1004
	}

1005
	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1006 1007 1008 1009 1010 1011 1012 1013
		int flags;

		flags = SG_MITER_ATOMIC;
		if (host->data->flags & MMC_DATA_READ)
			flags |= SG_MITER_TO_SG;
		else
			flags |= SG_MITER_FROM_SG;
		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1014
		host->blocks = data->blocks;
1015
	}
1016

1017 1018
	sdhci_set_transfer_irqs(host);

1019
	/* Set the DMA boundary value and block size */
1020 1021
	sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
		     SDHCI_BLOCK_SIZE);
1022
	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1023 1024
}

1025 1026 1027
static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
				    struct mmc_request *mrq)
{
1028 1029
	return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
	       !mrq->cap_cmd_during_tfr;
1030 1031
}

1032
static void sdhci_set_transfer_mode(struct sdhci_host *host,
1033
	struct mmc_command *cmd)
1034
{
1035
	u16 mode = 0;
1036
	struct mmc_data *data = cmd->data;
1037

1038
	if (data == NULL) {
1039 1040
		if (host->quirks2 &
			SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1041 1042 1043
			/* must not clear SDHCI_TRANSFER_MODE when tuning */
			if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
				sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1044
		} else {
1045
		/* clear Auto CMD settings for no data CMDs */
1046 1047
			mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
			sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1048
				SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1049
		}
1050
		return;
1051
	}
1052

1053 1054
	WARN_ON(!host->data);

1055 1056 1057
	if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
		mode = SDHCI_TRNS_BLK_CNT_EN;

1058
	if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1059
		mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1060 1061 1062 1063
		/*
		 * If we are sending CMD23, CMD12 never gets sent
		 * on successful completion (so no Auto-CMD12).
		 */
1064
		if (sdhci_auto_cmd12(host, cmd->mrq) &&
1065
		    (cmd->opcode != SD_IO_RW_EXTENDED))
1066
			mode |= SDHCI_TRNS_AUTO_CMD12;
1067
		else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
1068
			mode |= SDHCI_TRNS_AUTO_CMD23;
1069
			sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1070
		}
1071
	}
1072

1073 1074
	if (data->flags & MMC_DATA_READ)
		mode |= SDHCI_TRNS_READ;
1075
	if (host->flags & SDHCI_REQ_USE_DMA)
1076 1077
		mode |= SDHCI_TRNS_DMA;

1078
	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1079 1080
}

1081 1082 1083 1084 1085
static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
{
	return (!(host->flags & SDHCI_DEVICE_DEAD) &&
		((mrq->cmd && mrq->cmd->error) ||
		 (mrq->sbc && mrq->sbc->error) ||
1086
		 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1087 1088 1089
		 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
}

1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
{
	int i;

	for (i = 0; i < SDHCI_MAX_MRQS; i++) {
		if (host->mrqs_done[i] == mrq) {
			WARN_ON(1);
			return;
		}
	}

	for (i = 0; i < SDHCI_MAX_MRQS; i++) {
		if (!host->mrqs_done[i]) {
			host->mrqs_done[i] = mrq;
			break;
		}
	}

	WARN_ON(i >= SDHCI_MAX_MRQS);

	tasklet_schedule(&host->finish_tasklet);
}

1113 1114
static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
{
1115 1116 1117 1118 1119 1120 1121 1122 1123
	if (host->cmd && host->cmd->mrq == mrq)
		host->cmd = NULL;

	if (host->data_cmd && host->data_cmd->mrq == mrq)
		host->data_cmd = NULL;

	if (host->data && host->data->mrq == mrq)
		host->data = NULL;

1124 1125 1126
	if (sdhci_needs_reset(host, mrq))
		host->pending_reset = true;

1127
	__sdhci_finish_mrq(host, mrq);
1128 1129
}

1130 1131
static void sdhci_finish_data(struct sdhci_host *host)
{
1132 1133
	struct mmc_command *data_cmd = host->data_cmd;
	struct mmc_data *data = host->data;
1134 1135

	host->data = NULL;
1136
	host->data_cmd = NULL;
1137

1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
	/*
	 * The controller needs a reset of internal state machines upon error
	 * conditions.
	 */
	if (data->error) {
		if (!host->cmd || host->cmd == data_cmd)
			sdhci_do_reset(host, SDHCI_RESET_CMD);
		sdhci_do_reset(host, SDHCI_RESET_DATA);
	}

1148 1149 1150
	if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
	    (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
		sdhci_adma_table_post(host, data);
1151 1152

	/*
1153 1154 1155 1156 1157
	 * The specification states that the block count register must
	 * be updated, but it does not specify at what point in the
	 * data flow. That makes the register entirely useless to read
	 * back so we have to assume that nothing made it to the card
	 * in the event of an error.
1158
	 */
1159 1160
	if (data->error)
		data->bytes_xfered = 0;
1161
	else
1162
		data->bytes_xfered = data->blksz * data->blocks;
1163

1164 1165 1166 1167 1168 1169 1170
	/*
	 * Need to send CMD12 if -
	 * a) open-ended multiblock transfer (no CMD23)
	 * b) error in multiblock transfer
	 */
	if (data->stop &&
	    (data->error ||
1171
	     !data->mrq->sbc)) {
1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
		/*
		 * 'cap_cmd_during_tfr' request must not use the command line
		 * after mmc_command_done() has been called. It is upper layer's
		 * responsibility to send the stop command if required.
		 */
		if (data->mrq->cap_cmd_during_tfr) {
			sdhci_finish_mrq(host, data->mrq);
		} else {
			/* Avoid triggering warning in sdhci_send_command() */
			host->cmd = NULL;
			sdhci_send_command(host, data->stop);
		}
1184 1185 1186
	} else {
		sdhci_finish_mrq(host, data->mrq);
	}
1187 1188
}

1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205
static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
			    unsigned long timeout)
{
	if (sdhci_data_line_cmd(mrq->cmd))
		mod_timer(&host->data_timer, timeout);
	else
		mod_timer(&host->timer, timeout);
}

static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
{
	if (sdhci_data_line_cmd(mrq->cmd))
		del_timer(&host->data_timer);
	else
		del_timer(&host->timer);
}

1206
void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1207 1208
{
	int flags;
1209
	u32 mask;
1210
	unsigned long timeout;
1211 1212 1213

	WARN_ON(host->cmd);

1214 1215 1216
	/* Initially, a command has no error */
	cmd->error = 0;

1217 1218 1219 1220
	if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
	    cmd->opcode == MMC_STOP_TRANSMISSION)
		cmd->flags |= MMC_RSP_BUSY;

1221
	/* Wait max 10 ms */
1222
	timeout = 10;
1223 1224

	mask = SDHCI_CMD_INHIBIT;
1225
	if (sdhci_data_line_cmd(cmd))
1226 1227 1228 1229
		mask |= SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
1230
	if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1231 1232
		mask &= ~SDHCI_DATA_INHIBIT;

1233
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1234
		if (timeout == 0) {
1235 1236
			pr_err("%s: Controller never released inhibit bit(s).\n",
			       mmc_hostname(host->mmc));
1237
			sdhci_dumpregs(host);
1238
			cmd->error = -EIO;
1239
			sdhci_finish_mrq(host, cmd->mrq);
1240 1241
			return;
		}
1242 1243 1244
		timeout--;
		mdelay(1);
	}
1245 1246

	host->cmd = cmd;
1247
	if (sdhci_data_line_cmd(cmd)) {
1248 1249 1250
		WARN_ON(host->data_cmd);
		host->data_cmd = cmd;
	}
1251

1252
	sdhci_prepare_data(host, cmd);
1253

1254
	sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1255

1256
	sdhci_set_transfer_mode(host, cmd);
1257

1258
	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1259
		pr_err("%s: Unsupported response type!\n",
1260
			mmc_hostname(host->mmc));
1261
		cmd->error = -EINVAL;
1262
		sdhci_finish_mrq(host, cmd->mrq);
1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278
		return;
	}

	if (!(cmd->flags & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->flags & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->flags & MMC_RSP_BUSY)
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
	else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->flags & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->flags & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
1279 1280

	/* CMD19 is special in that the Data Present Select should be set */
1281 1282
	if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
	    cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1283 1284
		flags |= SDHCI_CMD_DATA;

1285 1286 1287 1288 1289 1290 1291 1292 1293
	timeout = jiffies;
	if (host->data_timeout)
		timeout += nsecs_to_jiffies(host->data_timeout);
	else if (!cmd->data && cmd->busy_timeout > 9000)
		timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
	else
		timeout += 10 * HZ;
	sdhci_mod_timer(host, cmd->mrq, timeout);

1294
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1295
}
1296
EXPORT_SYMBOL_GPL(sdhci_send_command);
1297

1298 1299 1300 1301 1302 1303 1304 1305 1306
static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
{
	int i, reg;

	for (i = 0; i < 4; i++) {
		reg = SDHCI_RESPONSE + (3 - i) * 4;
		cmd->resp[i] = sdhci_readl(host, reg);
	}

1307 1308 1309
	if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
		return;

1310 1311 1312 1313 1314 1315 1316 1317
	/* CRC is stripped so we need to do some shifting */
	for (i = 0; i < 4; i++) {
		cmd->resp[i] <<= 8;
		if (i != 3)
			cmd->resp[i] |= cmd->resp[i + 1] >> 24;
	}
}

1318 1319
static void sdhci_finish_command(struct sdhci_host *host)
{
1320
	struct mmc_command *cmd = host->cmd;
1321

1322 1323 1324 1325
	host->cmd = NULL;

	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136) {
1326
			sdhci_read_rsp_136(host, cmd);
1327
		} else {
1328
			cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1329 1330 1331
		}
	}

1332 1333 1334
	if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
		mmc_command_done(host->mmc, cmd->mrq);

1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	/*
	 * The host can send and interrupt when the busy state has
	 * ended, allowing us to wait without wasting CPU cycles.
	 * The busy signal uses DAT0 so this is similar to waiting
	 * for data to complete.
	 *
	 * Note: The 1.0 specification is a bit ambiguous about this
	 *       feature so there might be some problems with older
	 *       controllers.
	 */
1345 1346
	if (cmd->flags & MMC_RSP_BUSY) {
		if (cmd->data) {
1347 1348
			DBG("Cannot wait for busy signal when also doing a data transfer");
		} else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1349 1350
			   cmd == host->data_cmd) {
			/* Command complete before busy is ended */
1351 1352 1353 1354
			return;
		}
	}

1355
	/* Finished CMD23, now send actual command. */
1356 1357
	if (cmd == cmd->mrq->sbc) {
		sdhci_send_command(host, cmd->mrq->cmd);
1358
	} else {
1359

1360 1361 1362
		/* Processed actual command. */
		if (host->data && host->data_early)
			sdhci_finish_data(host);
1363

1364
		if (!cmd->data)
1365
			sdhci_finish_mrq(host, cmd->mrq);
1366
	}
1367 1368
}

1369 1370
static u16 sdhci_get_preset_value(struct sdhci_host *host)
{
1371
	u16 preset = 0;
1372

1373 1374
	switch (host->timing) {
	case MMC_TIMING_UHS_SDR12:
1375 1376
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
		break;
1377
	case MMC_TIMING_UHS_SDR25:
1378 1379
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
		break;
1380
	case MMC_TIMING_UHS_SDR50:
1381 1382
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
		break;
1383 1384
	case MMC_TIMING_UHS_SDR104:
	case MMC_TIMING_MMC_HS200:
1385 1386
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
		break;
1387
	case MMC_TIMING_UHS_DDR50:
1388
	case MMC_TIMING_MMC_DDR52:
1389 1390
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
		break;
1391 1392 1393
	case MMC_TIMING_MMC_HS400:
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
		break;
1394 1395 1396 1397 1398 1399 1400 1401 1402
	default:
		pr_warn("%s: Invalid UHS-I mode selected\n",
			mmc_hostname(host->mmc));
		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
		break;
	}
	return preset;
}

1403 1404
u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
		   unsigned int *actual_clock)
1405
{
1406
	int div = 0; /* Initialized for compiler warning */
1407
	int real_div = div, clk_mul = 1;
1408
	u16 clk = 0;
1409
	bool switch_base_clk = false;
1410

1411
	if (host->version >= SDHCI_SPEC_300) {
1412
		if (host->preset_enabled) {
1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429
			u16 pre_val;

			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
			pre_val = sdhci_get_preset_value(host);
			div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
				>> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
			if (host->clk_mul &&
				(pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
				clk = SDHCI_PROG_CLOCK_MODE;
				real_div = div + 1;
				clk_mul = host->clk_mul;
			} else {
				real_div = max_t(int, 1, div << 1);
			}
			goto clock_set;
		}

1430 1431 1432 1433 1434
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
1435 1436 1437 1438 1439
			for (div = 1; div <= 1024; div++) {
				if ((host->max_clk * host->clk_mul / div)
					<= clock)
					break;
			}
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458
			if ((host->max_clk * host->clk_mul / div) <= clock) {
				/*
				 * Set Programmable Clock Mode in the Clock
				 * Control register.
				 */
				clk = SDHCI_PROG_CLOCK_MODE;
				real_div = div;
				clk_mul = host->clk_mul;
				div--;
			} else {
				/*
				 * Divisor can be too small to reach clock
				 * speed requirement. Then use the base clock.
				 */
				switch_base_clk = true;
			}
		}

		if (!host->clk_mul || switch_base_clk) {
1459 1460 1461 1462 1463 1464 1465 1466 1467
			/* Version 3.00 divisors must be a multiple of 2. */
			if (host->max_clk <= clock)
				div = 1;
			else {
				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((host->max_clk / div) <= clock)
						break;
				}
1468
			}
1469
			real_div = div;
1470
			div >>= 1;
1471 1472 1473
			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
				&& !div && host->max_clk <= 25000000)
				div = 1;
1474 1475 1476
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
1477
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1478 1479 1480
			if ((host->max_clk / div) <= clock)
				break;
		}
1481
		real_div = div;
1482
		div >>= 1;
1483 1484
	}

1485
clock_set:
1486
	if (real_div)
1487
		*actual_clock = (host->max_clk * clk_mul) / real_div;
1488
	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1489 1490
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
1491 1492 1493 1494 1495

	return clk;
}
EXPORT_SYMBOL_GPL(sdhci_calc_clk);

1496
void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1497
{
1498
	ktime_t timeout;
1499

1500
	clk |= SDHCI_CLOCK_INT_EN;
1501
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1502

1503
	/* Wait max 20 ms */
1504
	timeout = ktime_add_ms(ktime_get(), 20);
1505 1506 1507 1508 1509 1510 1511
	while (1) {
		bool timedout = ktime_after(ktime_get(), timeout);

		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		if (clk & SDHCI_CLOCK_INT_STABLE)
			break;
		if (timedout) {
1512 1513
			pr_err("%s: Internal clock never stabilised.\n",
			       mmc_hostname(host->mmc));
1514 1515 1516
			sdhci_dumpregs(host);
			return;
		}
1517
		udelay(10);
1518
	}
1519 1520

	clk |= SDHCI_CLOCK_CARD_EN;
1521
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1522
}
1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
EXPORT_SYMBOL_GPL(sdhci_enable_clk);

void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
	u16 clk;

	host->mmc->actual_clock = 0;

	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return;

	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
	sdhci_enable_clk(host, clk);
}
1539
EXPORT_SYMBOL_GPL(sdhci_set_clock);
1540

1541 1542
static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
				unsigned short vdd)
1543
{
1544
	struct mmc_host *mmc = host->mmc;
1545 1546 1547 1548 1549 1550 1551 1552 1553

	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);

	if (mode != MMC_POWER_OFF)
		sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
	else
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
}

1554 1555
void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
			   unsigned short vdd)
1556
{
1557
	u8 pwr = 0;
1558

1559 1560
	if (mode != MMC_POWER_OFF) {
		switch (1 << vdd) {
1561
		case MMC_VDD_165_195:
1562 1563 1564 1565 1566 1567 1568
		/*
		 * Without a regulator, SDHCI does not support 2.0v
		 * so we only get here if the driver deliberately
		 * added the 2.0v range to ocr_avail. Map it to 1.8v
		 * for the purpose of turning on the power.
		 */
		case MMC_VDD_20_21:
1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		default:
1580 1581 1582
			WARN(1, "%s: Invalid vdd %#x\n",
			     mmc_hostname(host->mmc), vdd);
			break;
1583 1584 1585 1586
		}
	}

	if (host->pwr == pwr)
1587
		return;
1588

1589 1590 1591
	host->pwr = pwr;

	if (pwr == 0) {
1592
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1593 1594
		if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
			sdhci_runtime_pm_bus_off(host);
1595 1596 1597 1598 1599 1600 1601
	} else {
		/*
		 * Spec says that we should clear the power reg before setting
		 * a new value. Some controllers don't seem to like this though.
		 */
		if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
			sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1602

1603 1604 1605 1606 1607 1608 1609
		/*
		 * At least the Marvell CaFe chip gets confused if we set the
		 * voltage and set turn on power at the same time, so set the
		 * voltage first.
		 */
		if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
			sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1610

1611
		pwr |= SDHCI_POWER_ON;
1612

1613
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1614

1615 1616
		if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
			sdhci_runtime_pm_bus_on(host);
1617

1618 1619 1620 1621 1622 1623 1624
		/*
		 * Some controllers need an extra 10ms delay of 10ms before
		 * they can apply clock after applying power
		 */
		if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
			mdelay(10);
	}
1625
}
1626
EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1627

1628 1629
void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
		     unsigned short vdd)
1630
{
1631 1632
	if (IS_ERR(host->mmc->supply.vmmc))
		sdhci_set_power_noreg(host, mode, vdd);
1633
	else
1634
		sdhci_set_power_reg(host, mode, vdd);
1635
}
1636
EXPORT_SYMBOL_GPL(sdhci_set_power);
1637

1638 1639 1640 1641 1642 1643 1644 1645 1646
/*****************************************************************************\
 *                                                                           *
 * MMC callbacks                                                             *
 *                                                                           *
\*****************************************************************************/

static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct sdhci_host *host;
1647
	int present;
1648 1649 1650 1651
	unsigned long flags;

	host = mmc_priv(mmc);

1652
	/* Firstly check card presence */
1653
	present = mmc->ops->get_cd(mmc);
1654

1655 1656
	spin_lock_irqsave(&host->lock, flags);

1657
	sdhci_led_activate(host);
1658 1659 1660 1661 1662

	/*
	 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
	 * requests if Auto-CMD12 is enabled.
	 */
1663
	if (sdhci_auto_cmd12(host, mrq)) {
1664 1665 1666 1667 1668
		if (mrq->stop) {
			mrq->data->stop = NULL;
			mrq->stop = NULL;
		}
	}
1669

1670
	if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1671
		mrq->cmd->error = -ENOMEDIUM;
1672
		sdhci_finish_mrq(host, mrq);
1673
	} else {
1674
		if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1675 1676 1677
			sdhci_send_command(host, mrq->sbc);
		else
			sdhci_send_command(host, mrq->cmd);
1678
	}
1679

1680
	mmiowb();
1681 1682 1683
	spin_unlock_irqrestore(&host->lock, flags);
}

1684 1685 1686 1687 1688 1689 1690
void sdhci_set_bus_width(struct sdhci_host *host, int width)
{
	u8 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (width == MMC_BUS_WIDTH_8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
1691
		ctrl |= SDHCI_CTRL_8BITBUS;
1692
	} else {
1693
		if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
EXPORT_SYMBOL_GPL(sdhci_set_bus_width);

1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
{
	u16 ctrl_2;

	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	if ((timing == MMC_TIMING_MMC_HS200) ||
	    (timing == MMC_TIMING_UHS_SDR104))
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
	else if (timing == MMC_TIMING_UHS_SDR12)
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1716 1717 1718
	else if (timing == MMC_TIMING_SD_HS ||
		 timing == MMC_TIMING_MMC_HS ||
		 timing == MMC_TIMING_UHS_SDR25)
1719 1720 1721 1722 1723 1724
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
	else if (timing == MMC_TIMING_UHS_SDR50)
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
	else if ((timing == MMC_TIMING_UHS_DDR50) ||
		 (timing == MMC_TIMING_MMC_DDR52))
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1725 1726
	else if (timing == MMC_TIMING_MMC_HS400)
		ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1727 1728 1729 1730
	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);

1731
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1732
{
1733
	struct sdhci_host *host = mmc_priv(mmc);
1734 1735
	u8 ctrl;

1736 1737 1738
	if (ios->power_mode == MMC_POWER_UNDEFINED)
		return;

1739
	if (host->flags & SDHCI_DEVICE_DEAD) {
1740 1741
		if (!IS_ERR(mmc->supply.vmmc) &&
		    ios->power_mode == MMC_POWER_OFF)
1742
			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1743 1744
		return;
	}
Pierre Ossman's avatar
Pierre Ossman committed
1745

1746 1747 1748 1749 1750
	/*
	 * Reset the chip on each power off.
	 * Should clear out any weird states.
	 */
	if (ios->power_mode == MMC_POWER_OFF) {
1751
		sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1752
		sdhci_reinit(host);
1753 1754
	}

1755
	if (host->version >= SDHCI_SPEC_300 &&
1756 1757
		(ios->power_mode == MMC_POWER_UP) &&
		!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1758 1759
		sdhci_enable_preset_value(host, false);

1760
	if (!ios->clock || ios->clock != host->clock) {
1761
		host->ops->set_clock(host, ios->clock);
1762
		host->clock = ios->clock;
1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774

		if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
		    host->clock) {
			host->timeout_clk = host->mmc->actual_clock ?
						host->mmc->actual_clock / 1000 :
						host->clock / 1000;
			host->mmc->max_busy_timeout =
				host->ops->get_max_timeout_count ?
				host->ops->get_max_timeout_count(host) :
				1 << 27;
			host->mmc->max_busy_timeout /= host->timeout_clk;
		}
1775
	}
1776

1777 1778 1779 1780
	if (host->ops->set_power)
		host->ops->set_power(host, ios->power_mode, ios->vdd);
	else
		sdhci_set_power(host, ios->power_mode, ios->vdd);
1781

1782 1783 1784
	if (host->ops->platform_send_init_74_clocks)
		host->ops->platform_send_init_74_clocks(host, ios->power_mode);

1785
	host->ops->set_bus_width(host, ios->bus_width);
1786

1787
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1788

1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802
	if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
		if (ios->timing == MMC_TIMING_SD_HS ||
		     ios->timing == MMC_TIMING_MMC_HS ||
		     ios->timing == MMC_TIMING_MMC_HS400 ||
		     ios->timing == MMC_TIMING_MMC_HS200 ||
		     ios->timing == MMC_TIMING_MMC_DDR52 ||
		     ios->timing == MMC_TIMING_UHS_SDR50 ||
		     ios->timing == MMC_TIMING_UHS_SDR104 ||
		     ios->timing == MMC_TIMING_UHS_DDR50 ||
		     ios->timing == MMC_TIMING_UHS_SDR25)
			ctrl |= SDHCI_CTRL_HISPD;
		else
			ctrl &= ~SDHCI_CTRL_HISPD;
	}
1803

1804
	if (host->version >= SDHCI_SPEC_300) {
1805 1806
		u16 clk, ctrl_2;

1807
		if (!host->preset_enabled) {
1808
			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1809 1810 1811 1812
			/*
			 * We only need to set Driver Strength if the
			 * preset value enable is not set.
			 */
1813
			ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1814 1815 1816
			ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
			if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1817 1818
			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1819 1820
			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1821 1822 1823
			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
			else {
1824 1825
				pr_warn("%s: invalid driver type, default to driver type B\n",
					mmc_hostname(mmc));
1826 1827
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
			}
1828 1829

			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
		} else {
			/*
			 * According to SDHC Spec v3.00, if the Preset Value
			 * Enable in the Host Control 2 register is set, we
			 * need to reset SD Clock Enable before changing High
			 * Speed Enable to avoid generating clock gliches.
			 */

			/* Reset SD Clock Enable */
			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
			clk &= ~SDHCI_CLOCK_CARD_EN;
			sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

			/* Re-enable SD Clock */
1846
			host->ops->set_clock(host, host->clock);
1847
		}
1848 1849 1850 1851 1852 1853

		/* Reset SD Clock Enable */
		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		clk &= ~SDHCI_CLOCK_CARD_EN;
		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

1854
		host->ops->set_uhs_signaling(host, ios->timing);
1855
		host->timing = ios->timing;
1856

1857 1858 1859 1860 1861
		if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
				((ios->timing == MMC_TIMING_UHS_SDR12) ||
				 (ios->timing == MMC_TIMING_UHS_SDR25) ||
				 (ios->timing == MMC_TIMING_UHS_SDR50) ||
				 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1862 1863
				 (ios->timing == MMC_TIMING_UHS_DDR50) ||
				 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1864 1865 1866 1867 1868 1869 1870 1871
			u16 preset;

			sdhci_enable_preset_value(host, true);
			preset = sdhci_get_preset_value(host);
			ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
				>> SDHCI_PRESET_DRV_SHIFT;
		}

1872
		/* Re-enable SD Clock */
1873
		host->ops->set_clock(host, host->clock);
1874 1875
	} else
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1876

1877 1878 1879 1880 1881
	/*
	 * Some (ENE) controllers go apeshit on some ios operation,
	 * signalling timeout and CRC errors even on CMD0. Resetting
	 * it on each ios seems to solve the problem.
	 */
1882
	if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1883
		sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1884

1885
	mmiowb();
1886
}
1887
EXPORT_SYMBOL_GPL(sdhci_set_ios);
1888

1889
static int sdhci_get_cd(struct mmc_host *mmc)
1890 1891
{
	struct sdhci_host *host = mmc_priv(mmc);
1892
	int gpio_cd = mmc_gpio_get_cd(mmc);
1893 1894 1895 1896

	if (host->flags & SDHCI_DEVICE_DEAD)
		return 0;

1897
	/* If nonremovable, assume that the card is always present. */
1898
	if (!mmc_card_is_removable(host->mmc))
1899 1900
		return 1;

1901 1902 1903 1904
	/*
	 * Try slot gpio detect, if defined it take precedence
	 * over build in controller functionality
	 */
1905
	if (gpio_cd >= 0)
1906 1907
		return !!gpio_cd;

1908 1909 1910 1911
	/* If polling, assume that the card is always present. */
	if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
		return 1;

1912 1913 1914 1915
	/* Host native card detect */
	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
}

1916
static int sdhci_check_ro(struct sdhci_host *host)
1917 1918
{
	unsigned long flags;
1919
	int is_readonly;
1920 1921 1922

	spin_lock_irqsave(&host->lock, flags);

Pierre Ossman's avatar
Pierre Ossman committed
1923
	if (host->flags & SDHCI_DEVICE_DEAD)
1924 1925 1926
		is_readonly = 0;
	else if (host->ops->get_ro)
		is_readonly = host->ops->get_ro(host);
Pierre Ossman's avatar
Pierre Ossman committed
1927
	else
1928 1929
		is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
				& SDHCI_WRITE_PROTECT);
1930 1931 1932

	spin_unlock_irqrestore(&host->lock, flags);

1933 1934 1935
	/* This quirk needs to be replaced by a callback-function later */
	return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
		!is_readonly : is_readonly;
1936 1937
}

1938 1939
#define SAMPLE_COUNT	5

1940
static int sdhci_get_ro(struct mmc_host *mmc)
1941
{
1942
	struct sdhci_host *host = mmc_priv(mmc);
1943 1944 1945
	int i, ro_count;

	if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1946
		return sdhci_check_ro(host);
1947 1948 1949

	ro_count = 0;
	for (i = 0; i < SAMPLE_COUNT; i++) {
1950
		if (sdhci_check_ro(host)) {
1951 1952 1953 1954 1955 1956 1957 1958
			if (++ro_count > SAMPLE_COUNT / 2)
				return 1;
		}
		msleep(30);
	}
	return 0;
}

1959 1960 1961 1962 1963 1964 1965 1966
static void sdhci_hw_reset(struct mmc_host *mmc)
{
	struct sdhci_host *host = mmc_priv(mmc);

	if (host->ops && host->ops->hw_reset)
		host->ops->hw_reset(host);
}

1967 1968
static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
{
1969
	if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1970
		if (enable)
1971
			host->ier |= SDHCI_INT_CARD_INT;
1972
		else
1973 1974 1975 1976
			host->ier &= ~SDHCI_INT_CARD_INT;

		sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
		sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1977 1978
		mmiowb();
	}
1979 1980
}

1981
void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1982 1983 1984
{
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;
1985

1986 1987 1988
	if (enable)
		pm_runtime_get_noresume(host->mmc->parent);

1989
	spin_lock_irqsave(&host->lock, flags);
1990 1991 1992 1993 1994
	if (enable)
		host->flags |= SDHCI_SDIO_IRQ_ENABLED;
	else
		host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;

1995
	sdhci_enable_sdio_irq_nolock(host, enable);
1996
	spin_unlock_irqrestore(&host->lock, flags);
1997 1998 1999

	if (!enable)
		pm_runtime_put_noidle(host->mmc->parent);
2000
}
2001
EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2002

2003 2004
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
				      struct mmc_ios *ios)
2005
{
2006
	struct sdhci_host *host = mmc_priv(mmc);
2007
	u16 ctrl;
2008
	int ret;
2009

2010 2011 2012 2013 2014 2015
	/*
	 * Signal Voltage Switching is only applicable for Host Controllers
	 * v3.00 and above.
	 */
	if (host->version < SDHCI_SPEC_300)
		return 0;
2016

2017 2018
	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

2019
	switch (ios->signal_voltage) {
2020
	case MMC_SIGNAL_VOLTAGE_330:
2021 2022
		if (!(host->flags & SDHCI_SIGNALING_330))
			return -EINVAL;
2023 2024 2025
		/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
		ctrl &= ~SDHCI_CTRL_VDD_180;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2026

2027
		if (!IS_ERR(mmc->supply.vqmmc)) {
2028
			ret = mmc_regulator_set_vqmmc(mmc, ios);
2029
			if (ret) {
2030 2031
				pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
					mmc_hostname(mmc));
2032 2033 2034 2035 2036
				return -EIO;
			}
		}
		/* Wait for 5ms */
		usleep_range(5000, 5500);
2037

2038 2039 2040 2041
		/* 3.3V regulator output should be stable within 5 ms */
		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (!(ctrl & SDHCI_CTRL_VDD_180))
			return 0;
2042

2043 2044
		pr_warn("%s: 3.3V regulator output did not became stable\n",
			mmc_hostname(mmc));
2045 2046 2047

		return -EAGAIN;
	case MMC_SIGNAL_VOLTAGE_180:
2048 2049
		if (!(host->flags & SDHCI_SIGNALING_180))
			return -EINVAL;
2050
		if (!IS_ERR(mmc->supply.vqmmc)) {
2051
			ret = mmc_regulator_set_vqmmc(mmc, ios);
2052
			if (ret) {
2053 2054
				pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
					mmc_hostname(mmc));
2055 2056 2057
				return -EIO;
			}
		}
2058 2059 2060 2061 2062

		/*
		 * Enable 1.8V Signal Enable in the Host Control2
		 * register
		 */
2063 2064
		ctrl |= SDHCI_CTRL_VDD_180;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2065

2066 2067 2068 2069
		/* Some controller need to do more when switching */
		if (host->ops->voltage_switch)
			host->ops->voltage_switch(host);

2070 2071 2072 2073
		/* 1.8V regulator output should be stable within 5 ms */
		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (ctrl & SDHCI_CTRL_VDD_180)
			return 0;
2074

2075 2076
		pr_warn("%s: 1.8V regulator output did not became stable\n",
			mmc_hostname(mmc));
2077

2078 2079
		return -EAGAIN;
	case MMC_SIGNAL_VOLTAGE_120:
2080 2081
		if (!(host->flags & SDHCI_SIGNALING_120))
			return -EINVAL;
2082
		if (!IS_ERR(mmc->supply.vqmmc)) {
2083
			ret = mmc_regulator_set_vqmmc(mmc, ios);
2084
			if (ret) {
2085 2086
				pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
					mmc_hostname(mmc));
2087
				return -EIO;
2088 2089
			}
		}
2090
		return 0;
2091
	default:
2092 2093
		/* No signal voltage switch required */
		return 0;
2094
	}
2095
}
2096
EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2097

2098 2099 2100 2101 2102
static int sdhci_card_busy(struct mmc_host *mmc)
{
	struct sdhci_host *host = mmc_priv(mmc);
	u32 present_state;

2103
	/* Check whether DAT[0] is 0 */
2104 2105
	present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);

2106
	return !(present_state & SDHCI_DATA_0_LVL_MASK);
2107 2108
}

2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->flags |= SDHCI_HS400_TUNING;
	spin_unlock_irqrestore(&host->lock, flags);

	return 0;
}

2121
void sdhci_start_tuning(struct sdhci_host *host)
2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
{
	u16 ctrl;

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	ctrl |= SDHCI_CTRL_EXEC_TUNING;
	if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
		ctrl |= SDHCI_CTRL_TUNED_CLK;
	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

	/*
	 * As per the Host Controller spec v3.00, tuning command
	 * generates Buffer Read Ready interrupt, so enable that.
	 *
	 * Note: The spec clearly says that when tuning sequence
	 * is being performed, the controller does not generate
	 * interrupts other than Buffer Read Ready interrupt. But
	 * to make sure we don't hit a controller bug, we _only_
	 * enable Buffer Read Ready interrupt here.
	 */
	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
}
2144
EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2145

2146
void sdhci_end_tuning(struct sdhci_host *host)
2147 2148 2149 2150
{
	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
2151
EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2152

2153
void sdhci_reset_tuning(struct sdhci_host *host)
2154 2155 2156 2157 2158 2159 2160 2161
{
	u16 ctrl;

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	ctrl &= ~SDHCI_CTRL_TUNED_CLK;
	ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
}
2162
EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2163

2164
static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182
{
	sdhci_reset_tuning(host);

	sdhci_do_reset(host, SDHCI_RESET_CMD);
	sdhci_do_reset(host, SDHCI_RESET_DATA);

	sdhci_end_tuning(host);

	mmc_abort_tuning(host->mmc, opcode);
}

/*
 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
 * tuning command does not have a data payload (or rather the hardware does it
 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
 * interrupt setup is different to other commands and there is no timeout
 * interrupt so special handling is needed.
 */
2183
void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2184 2185
{
	struct mmc_host *mmc = host->mmc;
2186 2187
	struct mmc_command cmd = {};
	struct mmc_request mrq = {};
2188
	unsigned long flags;
2189
	u32 b = host->sdma_boundary;
2190 2191

	spin_lock_irqsave(&host->lock, flags);
2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202

	cmd.opcode = opcode;
	cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
	cmd.mrq = &mrq;

	mrq.cmd = &cmd;
	/*
	 * In response to CMD19, the card sends 64 bytes of tuning
	 * block to the Host Controller. So we set the block size
	 * to 64 here.
	 */
2203 2204
	if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
	    mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2205
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2206
	else
2207
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224

	/*
	 * The tuning block is sent by the card to the host controller.
	 * So we set the TRNS_READ bit in the Transfer Mode register.
	 * This also takes care of setting DMA Enable and Multi Block
	 * Select in the same register to 0.
	 */
	sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);

	sdhci_send_command(host, &cmd);

	host->cmd = NULL;

	sdhci_del_timer(host, &mrq);

	host->tuning_done = 0;

2225
	mmiowb();
2226 2227 2228 2229 2230 2231 2232
	spin_unlock_irqrestore(&host->lock, flags);

	/* Wait for Buffer Read Ready interrupt */
	wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
			   msecs_to_jiffies(50));

}
2233
EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2234

2235
static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245
{
	int i;

	/*
	 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
	 * of loops reaches 40 times.
	 */
	for (i = 0; i < MAX_TUNING_LOOP; i++) {
		u16 ctrl;

2246
		sdhci_send_tuning(host, opcode);
2247 2248 2249 2250

		if (!host->tuning_done) {
			pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
				mmc_hostname(host->mmc));
2251
			sdhci_abort_tuning(host, opcode);
2252 2253 2254 2255 2256 2257 2258 2259 2260 2261
			return;
		}

		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
			if (ctrl & SDHCI_CTRL_TUNED_CLK)
				return; /* Success! */
			break;
		}

2262 2263 2264
		/* Spec does not require a delay between tuning cycles */
		if (host->tuning_delay > 0)
			mdelay(host->tuning_delay);
2265 2266 2267 2268 2269 2270 2271
	}

	pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
		mmc_hostname(host->mmc));
	sdhci_reset_tuning(host);
}

2272
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2273
{
2274
	struct sdhci_host *host = mmc_priv(mmc);
2275
	int err = 0;
2276
	unsigned int tuning_count = 0;
2277
	bool hs400_tuning;
2278

2279 2280
	hs400_tuning = host->flags & SDHCI_HS400_TUNING;

2281 2282 2283
	if (host->tuning_mode == SDHCI_TUNING_MODE_1)
		tuning_count = host->tuning_count;

2284
	/*
2285 2286 2287
	 * The Host Controller needs tuning in case of SDR104 and DDR50
	 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
	 * the Capabilities register.
2288 2289
	 * If the Host Controller supports the HS200 mode then the
	 * tuning function has to be executed.
2290
	 */
2291
	switch (host->timing) {
2292
	/* HS400 tuning is done in HS200 mode */
2293
	case MMC_TIMING_MMC_HS400:
2294
		err = -EINVAL;
2295
		goto out;
2296

2297
	case MMC_TIMING_MMC_HS200:
2298 2299 2300 2301 2302 2303 2304 2305
		/*
		 * Periodic re-tuning for HS400 is not expected to be needed, so
		 * disable it here.
		 */
		if (hs400_tuning)
			tuning_count = 0;
		break;

2306
	case MMC_TIMING_UHS_SDR104:
2307
	case MMC_TIMING_UHS_DDR50:
2308 2309 2310
		break;

	case MMC_TIMING_UHS_SDR50:
2311
		if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2312 2313 2314 2315
			break;
		/* FALLTHROUGH */

	default:
2316
		goto out;
2317 2318
	}

2319
	if (host->ops->platform_execute_tuning) {
2320
		err = host->ops->platform_execute_tuning(host, opcode);
2321
		goto out;
2322 2323
	}

2324
	host->mmc->retune_period = tuning_count;
2325

2326 2327 2328
	if (host->tuning_delay < 0)
		host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;

2329
	sdhci_start_tuning(host);
2330

2331
	__sdhci_execute_tuning(host, opcode);
2332

2333
	sdhci_end_tuning(host);
2334
out:
2335
	host->flags &= ~SDHCI_HS400_TUNING;
2336

2337 2338
	return err;
}
2339
EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2340

2341
static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2342 2343 2344 2345 2346 2347 2348 2349 2350
{
	/* Host Controller v3.00 defines preset value registers */
	if (host->version < SDHCI_SPEC_300)
		return;

	/*
	 * We only enable or disable Preset Value if they are not already
	 * enabled or disabled respectively. Otherwise, we bail out.
	 */
2351 2352 2353 2354 2355 2356 2357 2358
	if (host->preset_enabled != enable) {
		u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

		if (enable)
			ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
		else
			ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;

2359
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2360 2361 2362 2363 2364 2365 2366

		if (enable)
			host->flags |= SDHCI_PV_ENABLED;
		else
			host->flags &= ~SDHCI_PV_ENABLED;

		host->preset_enabled = enable;
2367
	}
2368 2369
}

2370 2371 2372 2373 2374 2375
static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
				int err)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;

2376
	if (data->host_cookie != COOKIE_UNMAPPED)
2377
		dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2378
			     mmc_get_dma_dir(data));
2379 2380

	data->host_cookie = COOKIE_UNMAPPED;
2381 2382
}

2383
static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2384 2385 2386
{
	struct sdhci_host *host = mmc_priv(mmc);

2387
	mrq->data->host_cookie = COOKIE_UNMAPPED;
2388

2389 2390 2391 2392 2393 2394
	/*
	 * No pre-mapping in the pre hook if we're using the bounce buffer,
	 * for that we would need two bounce buffers since one buffer is
	 * in flight when this is getting called.
	 */
	if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2395
		sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2396 2397
}

2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415
static inline bool sdhci_has_requests(struct sdhci_host *host)
{
	return host->cmd || host->data_cmd;
}

static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
{
	if (host->data_cmd) {
		host->data_cmd->error = err;
		sdhci_finish_mrq(host, host->data_cmd->mrq);
	}

	if (host->cmd) {
		host->cmd->error = err;
		sdhci_finish_mrq(host, host->cmd->mrq);
	}
}

2416
static void sdhci_card_event(struct mmc_host *mmc)
2417
{
2418
	struct sdhci_host *host = mmc_priv(mmc);
2419
	unsigned long flags;
2420
	int present;
2421

2422 2423 2424 2425
	/* First check if client has provided their own card event */
	if (host->ops->card_event)
		host->ops->card_event(host);

2426
	present = mmc->ops->get_cd(mmc);
2427

2428 2429
	spin_lock_irqsave(&host->lock, flags);

2430 2431
	/* Check sdhci_has_requests() first in case we are runtime suspended */
	if (sdhci_has_requests(host) && !present) {
2432
		pr_err("%s: Card removed during transfer!\n",
2433
			mmc_hostname(host->mmc));
2434
		pr_err("%s: Resetting controller.\n",
2435
			mmc_hostname(host->mmc));
2436

2437 2438
		sdhci_do_reset(host, SDHCI_RESET_CMD);
		sdhci_do_reset(host, SDHCI_RESET_DATA);
2439

2440
		sdhci_error_out_mrqs(host, -ENOMEDIUM);
2441 2442 2443
	}

	spin_unlock_irqrestore(&host->lock, flags);
2444 2445 2446 2447
}

static const struct mmc_host_ops sdhci_ops = {
	.request	= sdhci_request,
2448 2449
	.post_req	= sdhci_post_req,
	.pre_req	= sdhci_pre_req,
2450
	.set_ios	= sdhci_set_ios,
2451
	.get_cd		= sdhci_get_cd,
2452 2453 2454 2455
	.get_ro		= sdhci_get_ro,
	.hw_reset	= sdhci_hw_reset,
	.enable_sdio_irq = sdhci_enable_sdio_irq,
	.start_signal_voltage_switch	= sdhci_start_signal_voltage_switch,
2456
	.prepare_hs400_tuning		= sdhci_prepare_hs400_tuning,
2457 2458
	.execute_tuning			= sdhci_execute_tuning,
	.card_event			= sdhci_card_event,
2459
	.card_busy	= sdhci_card_busy,
2460 2461 2462 2463 2464 2465 2466 2467
};

/*****************************************************************************\
 *                                                                           *
 * Tasklets                                                                  *
 *                                                                           *
\*****************************************************************************/

2468
static bool sdhci_request_done(struct sdhci_host *host)
2469 2470 2471
{
	unsigned long flags;
	struct mmc_request *mrq;
2472
	int i;
2473

2474 2475
	spin_lock_irqsave(&host->lock, flags);

2476 2477
	for (i = 0; i < SDHCI_MAX_MRQS; i++) {
		mrq = host->mrqs_done[i];
2478
		if (mrq)
2479
			break;
2480
	}
2481

2482 2483 2484 2485
	if (!mrq) {
		spin_unlock_irqrestore(&host->lock, flags);
		return true;
	}
2486

2487 2488
	sdhci_del_timer(host, mrq);

2489 2490 2491 2492 2493 2494 2495 2496 2497
	/*
	 * Always unmap the data buffers if they were mapped by
	 * sdhci_prepare_data() whenever we finish with a request.
	 * This avoids leaking DMA mappings on error.
	 */
	if (host->flags & SDHCI_REQ_USE_DMA) {
		struct mmc_data *data = mrq->data;

		if (data && data->host_cookie == COOKIE_MAPPED) {
2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536
			if (host->bounce_buffer) {
				/*
				 * On reads, copy the bounced data into the
				 * sglist
				 */
				if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
					unsigned int length = data->bytes_xfered;

					if (length > host->bounce_buffer_size) {
						pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
						       mmc_hostname(host->mmc),
						       host->bounce_buffer_size,
						       data->bytes_xfered);
						/* Cap it down and continue */
						length = host->bounce_buffer_size;
					}
					dma_sync_single_for_cpu(
						host->mmc->parent,
						host->bounce_addr,
						host->bounce_buffer_size,
						DMA_FROM_DEVICE);
					sg_copy_from_buffer(data->sg,
						data->sg_len,
						host->bounce_buffer,
						length);
				} else {
					/* No copying, just switch ownership */
					dma_sync_single_for_cpu(
						host->mmc->parent,
						host->bounce_addr,
						host->bounce_buffer_size,
						mmc_get_dma_dir(data));
				}
			} else {
				/* Unmap the raw data */
				dma_unmap_sg(mmc_dev(host->mmc), data->sg,
					     data->sg_len,
					     mmc_get_dma_dir(data));
			}
2537 2538 2539 2540
			data->host_cookie = COOKIE_UNMAPPED;
		}
	}

2541 2542 2543 2544
	/*
	 * The controller needs a reset of internal state machines
	 * upon error conditions.
	 */
2545
	if (sdhci_needs_reset(host, mrq)) {
2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556
		/*
		 * Do not finish until command and data lines are available for
		 * reset. Note there can only be one other mrq, so it cannot
		 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
		 * would both be null.
		 */
		if (host->cmd || host->data_cmd) {
			spin_unlock_irqrestore(&host->lock, flags);
			return true;
		}

2557
		/* Some controllers need this kick or reset won't work here */
2558
		if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2559
			/* This is to force an update */
2560
			host->ops->set_clock(host, host->clock);
2561 2562 2563

		/* Spec says we should do both at the same time, but Ricoh
		   controllers do not like that. */
2564 2565
		sdhci_do_reset(host, SDHCI_RESET_CMD);
		sdhci_do_reset(host, SDHCI_RESET_DATA);
2566 2567

		host->pending_reset = false;
2568 2569
	}

2570 2571
	if (!sdhci_has_requests(host))
		sdhci_led_deactivate(host);
2572

2573 2574
	host->mrqs_done[i] = NULL;

2575
	mmiowb();
2576 2577 2578
	spin_unlock_irqrestore(&host->lock, flags);

	mmc_request_done(host->mmc, mrq);
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588

	return false;
}

static void sdhci_tasklet_finish(unsigned long param)
{
	struct sdhci_host *host = (struct sdhci_host *)param;

	while (!sdhci_request_done(host))
		;
2589 2590
}

2591
static void sdhci_timeout_timer(struct timer_list *t)
2592 2593 2594 2595
{
	struct sdhci_host *host;
	unsigned long flags;

2596
	host = from_timer(host, t, timer);
2597 2598 2599

	spin_lock_irqsave(&host->lock, flags);

2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612
	if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
		pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
		       mmc_hostname(host->mmc));
		sdhci_dumpregs(host);

		host->cmd->error = -ETIMEDOUT;
		sdhci_finish_mrq(host, host->cmd->mrq);
	}

	mmiowb();
	spin_unlock_irqrestore(&host->lock, flags);
}

2613
static void sdhci_timeout_data_timer(struct timer_list *t)
2614 2615 2616 2617
{
	struct sdhci_host *host;
	unsigned long flags;

2618
	host = from_timer(host, t, data_timer);
2619 2620 2621 2622 2623

	spin_lock_irqsave(&host->lock, flags);

	if (host->data || host->data_cmd ||
	    (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2624 2625
		pr_err("%s: Timeout waiting for hardware interrupt.\n",
		       mmc_hostname(host->mmc));
2626 2627 2628
		sdhci_dumpregs(host);

		if (host->data) {
2629
			host->data->error = -ETIMEDOUT;
2630
			sdhci_finish_data(host);
2631 2632 2633
		} else if (host->data_cmd) {
			host->data_cmd->error = -ETIMEDOUT;
			sdhci_finish_mrq(host, host->data_cmd->mrq);
2634
		} else {
2635 2636
			host->cmd->error = -ETIMEDOUT;
			sdhci_finish_mrq(host, host->cmd->mrq);
2637 2638 2639
		}
	}

2640
	mmiowb();
2641 2642 2643 2644 2645 2646 2647 2648 2649
	spin_unlock_irqrestore(&host->lock, flags);
}

/*****************************************************************************\
 *                                                                           *
 * Interrupt handling                                                        *
 *                                                                           *
\*****************************************************************************/

2650
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2651
{
2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666
	/* Handle auto-CMD12 error */
	if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
		struct mmc_request *mrq = host->data_cmd->mrq;
		u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
		int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
				   SDHCI_INT_DATA_TIMEOUT :
				   SDHCI_INT_DATA_CRC;

		/* Treat auto-CMD12 error the same as data error */
		if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
			*intmask_p |= data_err_bit;
			return;
		}
	}

2667
	if (!host->cmd) {
2668 2669 2670 2671 2672 2673 2674
		/*
		 * SDHCI recovers from errors by resetting the cmd and data
		 * circuits.  Until that is done, there very well might be more
		 * interrupts, so ignore them in that case.
		 */
		if (host->pending_reset)
			return;
2675 2676
		pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
		       mmc_hostname(host->mmc), (unsigned)intmask);
2677 2678 2679 2680
		sdhci_dumpregs(host);
		return;
	}

2681 2682 2683 2684 2685 2686
	if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
		       SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
		if (intmask & SDHCI_INT_TIMEOUT)
			host->cmd->error = -ETIMEDOUT;
		else
			host->cmd->error = -EILSEQ;
2687

2688
		/* Treat data command CRC error the same as data CRC error */
2689 2690 2691 2692
		if (host->cmd->data &&
		    (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
		     SDHCI_INT_CRC) {
			host->cmd = NULL;
2693
			*intmask_p |= SDHCI_INT_DATA_CRC;
2694 2695 2696
			return;
		}

2697
		sdhci_finish_mrq(host, host->cmd->mrq);
2698 2699 2700
		return;
	}

2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715
	/* Handle auto-CMD23 error */
	if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
		struct mmc_request *mrq = host->cmd->mrq;
		u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
		int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
			  -ETIMEDOUT :
			  -EILSEQ;

		if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
			mrq->sbc->error = err;
			sdhci_finish_mrq(host, mrq);
			return;
		}
	}

2716
	if (intmask & SDHCI_INT_RESPONSE)
2717
		sdhci_finish_command(host);
2718 2719
}

2720
static void sdhci_adma_show_error(struct sdhci_host *host)
2721
{
2722
	void *desc = host->adma_table;
2723
	dma_addr_t dma = host->adma_addr;
2724 2725 2726 2727

	sdhci_dumpregs(host);

	while (true) {
2728 2729 2730
		struct sdhci_adma2_64_desc *dma_desc = desc;

		if (host->flags & SDHCI_USE_64_BIT_DMA)
2731 2732 2733
			SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
			    (unsigned long long)dma,
			    le32_to_cpu(dma_desc->addr_hi),
2734 2735 2736 2737
			    le32_to_cpu(dma_desc->addr_lo),
			    le16_to_cpu(dma_desc->len),
			    le16_to_cpu(dma_desc->cmd));
		else
2738 2739 2740
			SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
			    (unsigned long long)dma,
			    le32_to_cpu(dma_desc->addr_lo),
2741 2742
			    le16_to_cpu(dma_desc->len),
			    le16_to_cpu(dma_desc->cmd));
2743

2744
		desc += host->desc_sz;
2745
		dma += host->desc_sz;
2746

2747
		if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2748 2749 2750 2751
			break;
	}
}

2752 2753
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
2754
	u32 command;
2755

2756 2757
	/* CMD19 generates _only_ Buffer Read Ready interrupt */
	if (intmask & SDHCI_INT_DATA_AVAIL) {
2758 2759 2760
		command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
		if (command == MMC_SEND_TUNING_BLOCK ||
		    command == MMC_SEND_TUNING_BLOCK_HS200) {
2761 2762 2763 2764 2765 2766
			host->tuning_done = 1;
			wake_up(&host->buf_ready_int);
			return;
		}
	}

2767
	if (!host->data) {
2768 2769
		struct mmc_command *data_cmd = host->data_cmd;

2770
		/*
2771 2772 2773
		 * The "data complete" interrupt is also used to
		 * indicate that a busy state has ended. See comment
		 * above in sdhci_cmd_irq().
2774
		 */
2775
		if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2776
			if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2777
				host->data_cmd = NULL;
2778
				data_cmd->error = -ETIMEDOUT;
2779
				sdhci_finish_mrq(host, data_cmd->mrq);
2780 2781
				return;
			}
2782
			if (intmask & SDHCI_INT_DATA_END) {
2783
				host->data_cmd = NULL;
2784 2785 2786 2787 2788
				/*
				 * Some cards handle busy-end interrupt
				 * before the command completed, so make
				 * sure we do things in the proper order.
				 */
2789 2790 2791
				if (host->cmd == data_cmd)
					return;

2792
				sdhci_finish_mrq(host, data_cmd->mrq);
2793 2794 2795
				return;
			}
		}
2796

2797 2798 2799 2800 2801 2802 2803 2804
		/*
		 * SDHCI recovers from errors by resetting the cmd and data
		 * circuits. Until that is done, there very well might be more
		 * interrupts, so ignore them in that case.
		 */
		if (host->pending_reset)
			return;

2805 2806
		pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
		       mmc_hostname(host->mmc), (unsigned)intmask);
2807 2808 2809 2810 2811 2812
		sdhci_dumpregs(host);

		return;
	}

	if (intmask & SDHCI_INT_DATA_TIMEOUT)
2813
		host->data->error = -ETIMEDOUT;
2814 2815 2816 2817 2818
	else if (intmask & SDHCI_INT_DATA_END_BIT)
		host->data->error = -EILSEQ;
	else if ((intmask & SDHCI_INT_DATA_CRC) &&
		SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
			!= MMC_BUS_TEST_R)
2819
		host->data->error = -EILSEQ;
2820
	else if (intmask & SDHCI_INT_ADMA_ERROR) {
2821 2822
		pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
		       intmask);
2823
		sdhci_adma_show_error(host);
2824
		host->data->error = -EIO;
2825 2826
		if (host->ops->adma_workaround)
			host->ops->adma_workaround(host, intmask);
2827
	}
2828

2829
	if (host->data->error)
2830 2831
		sdhci_finish_data(host);
	else {
Pierre Ossman's avatar
Pierre Ossman committed
2832
		if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2833 2834
			sdhci_transfer_pio(host);

2835 2836 2837 2838
		/*
		 * We currently don't do anything fancy with DMA
		 * boundaries, but as we can't disable the feature
		 * we need to at least restart the transfer.
2839 2840 2841 2842
		 *
		 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
		 * should return a valid address to continue from, but as
		 * some controllers are faulty, don't trust them.
2843
		 */
2844 2845
		if (intmask & SDHCI_INT_DMA_END) {
			u32 dmastart, dmanow;
2846 2847

			dmastart = sdhci_sdma_address(host);
2848 2849 2850 2851 2852 2853 2854 2855
			dmanow = dmastart + host->data->bytes_xfered;
			/*
			 * Force update to the next DMA block boundary.
			 */
			dmanow = (dmanow &
				~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
				SDHCI_DEFAULT_BOUNDARY_SIZE;
			host->data->bytes_xfered = dmanow - dmastart;
2856 2857
			DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
			    dmastart, host->data->bytes_xfered, dmanow);
2858 2859
			sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
		}
2860

2861
		if (intmask & SDHCI_INT_DATA_END) {
2862
			if (host->cmd == host->data_cmd) {
2863 2864 2865 2866 2867 2868 2869 2870 2871 2872
				/*
				 * Data managed to finish before the
				 * command completed. Make sure we do
				 * things in the proper order.
				 */
				host->data_early = 1;
			} else {
				sdhci_finish_data(host);
			}
		}
2873 2874 2875
	}
}

2876
static irqreturn_t sdhci_irq(int irq, void *dev_id)
2877
{
2878
	irqreturn_t result = IRQ_NONE;
2879
	struct sdhci_host *host = dev_id;
2880
	u32 intmask, mask, unexpected = 0;
2881
	int max_loops = 16;
2882 2883 2884

	spin_lock(&host->lock);

2885
	if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2886
		spin_unlock(&host->lock);
2887
		return IRQ_NONE;
2888 2889
	}

2890
	intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2891
	if (!intmask || intmask == 0xffffffff) {
2892 2893 2894 2895
		result = IRQ_NONE;
		goto out;
	}

2896
	do {
2897 2898 2899 2900 2901 2902 2903 2904
		DBG("IRQ status 0x%08x\n", intmask);

		if (host->ops->irq) {
			intmask = host->ops->irq(host, intmask);
			if (!intmask)
				goto cont;
		}

2905 2906 2907 2908
		/* Clear selected interrupts. */
		mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
				  SDHCI_INT_BUS_POWER);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
2909

2910 2911 2912
		if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
			u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
				      SDHCI_CARD_PRESENT;
2913

2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924
			/*
			 * There is a observation on i.mx esdhc.  INSERT
			 * bit will be immediately set again when it gets
			 * cleared, if a card is inserted.  We have to mask
			 * the irq to prevent interrupt storm which will
			 * freeze the system.  And the REMOVE gets the
			 * same situation.
			 *
			 * More testing are needed here to ensure it works
			 * for other platforms though.
			 */
2925 2926 2927 2928 2929 2930
			host->ier &= ~(SDHCI_INT_CARD_INSERT |
				       SDHCI_INT_CARD_REMOVE);
			host->ier |= present ? SDHCI_INT_CARD_REMOVE :
					       SDHCI_INT_CARD_INSERT;
			sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
			sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2931 2932 2933

			sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
				     SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2934 2935 2936 2937

			host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
						       SDHCI_INT_CARD_REMOVE);
			result = IRQ_WAKE_THREAD;
2938
		}
2939

2940
		if (intmask & SDHCI_INT_CMD_MASK)
2941
			sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
2942

2943 2944
		if (intmask & SDHCI_INT_DATA_MASK)
			sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2945

2946 2947 2948
		if (intmask & SDHCI_INT_BUS_POWER)
			pr_err("%s: Card is consuming too much power!\n",
				mmc_hostname(host->mmc));
2949

2950 2951 2952
		if (intmask & SDHCI_INT_RETUNE)
			mmc_retune_needed(host->mmc);

2953 2954
		if ((intmask & SDHCI_INT_CARD_INT) &&
		    (host->ier & SDHCI_INT_CARD_INT)) {
2955 2956 2957 2958
			sdhci_enable_sdio_irq_nolock(host, false);
			host->thread_isr |= SDHCI_INT_CARD_INT;
			result = IRQ_WAKE_THREAD;
		}
2959

2960 2961 2962
		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
			     SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
			     SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2963
			     SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2964

2965 2966 2967 2968
		if (intmask) {
			unexpected |= intmask;
			sdhci_writel(host, intmask, SDHCI_INT_STATUS);
		}
2969
cont:
2970 2971
		if (result == IRQ_NONE)
			result = IRQ_HANDLED;
2972

2973 2974
		intmask = sdhci_readl(host, SDHCI_INT_STATUS);
	} while (intmask && --max_loops);
2975 2976 2977
out:
	spin_unlock(&host->lock);

2978 2979 2980 2981 2982
	if (unexpected) {
		pr_err("%s: Unexpected interrupt 0x%08x.\n",
			   mmc_hostname(host->mmc), unexpected);
		sdhci_dumpregs(host);
	}
2983

2984 2985 2986
	return result;
}

2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997
static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
{
	struct sdhci_host *host = dev_id;
	unsigned long flags;
	u32 isr;

	spin_lock_irqsave(&host->lock, flags);
	isr = host->thread_isr;
	host->thread_isr = 0;
	spin_unlock_irqrestore(&host->lock, flags);

2998
	if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2999 3000 3001 3002
		struct mmc_host *mmc = host->mmc;

		mmc->ops->card_event(mmc);
		mmc_detect_change(mmc, msecs_to_jiffies(200));
3003 3004
	}

3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016
	if (isr & SDHCI_INT_CARD_INT) {
		sdio_run_irqs(host->mmc);

		spin_lock_irqsave(&host->lock, flags);
		if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
			sdhci_enable_sdio_irq_nolock(host, true);
		spin_unlock_irqrestore(&host->lock, flags);
	}

	return isr ? IRQ_HANDLED : IRQ_NONE;
}

3017 3018 3019 3020 3021 3022 3023
/*****************************************************************************\
 *                                                                           *
 * Suspend/resume                                                            *
 *                                                                           *
\*****************************************************************************/

#ifdef CONFIG_PM
3024 3025 3026 3027 3028 3029 3030 3031

static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
{
	return mmc_card_is_removable(host->mmc) &&
	       !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
	       !mmc_can_gpio_cd(host->mmc);
}

3032 3033 3034 3035 3036 3037 3038 3039
/*
 * To enable wakeup events, the corresponding events have to be enabled in
 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
 * Table' in the SD Host Controller Standard Specification.
 * It is useless to restore SDHCI_INT_ENABLE state in
 * sdhci_disable_irq_wakeups() since it will be set by
 * sdhci_enable_card_detection() or sdhci_init().
 */
3040
static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3041
{
3042 3043 3044 3045
	u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
		  SDHCI_WAKE_ON_INT;
	u32 irq_val = 0;
	u8 wake_val = 0;
3046 3047
	u8 val;

3048
	if (sdhci_cd_irq_can_wakeup(host)) {
3049 3050
		wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
		irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3051
	}
3052

3053 3054 3055 3056 3057 3058 3059
	if (mmc_card_wake_sdio_irq(host->mmc)) {
		wake_val |= SDHCI_WAKE_ON_INT;
		irq_val |= SDHCI_INT_CARD_INT;
	}

	if (!irq_val)
		return false;
3060 3061 3062 3063

	val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
	val &= ~mask;
	val |= wake_val;
3064
	sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3065

3066
	sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3067 3068 3069 3070

	host->irq_wake_enabled = !enable_irq_wake(host->irq);

	return host->irq_wake_enabled;
3071 3072
}

3073
static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3074 3075 3076 3077 3078 3079 3080 3081
{
	u8 val;
	u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
			| SDHCI_WAKE_ON_INT;

	val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
	val &= ~mask;
	sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3082 3083 3084 3085

	disable_irq_wake(host->irq);

	host->irq_wake_enabled = false;
3086
}
3087

3088
int sdhci_suspend_host(struct sdhci_host *host)
3089
{
3090 3091
	sdhci_disable_card_detection(host);

3092
	mmc_retune_timer_stop(host->mmc);
3093

3094 3095
	if (!device_may_wakeup(mmc_dev(host->mmc)) ||
	    !sdhci_enable_irq_wakeups(host)) {
3096 3097 3098
		host->ier = 0;
		sdhci_writel(host, 0, SDHCI_INT_ENABLE);
		sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3099 3100
		free_irq(host->irq, host);
	}
3101

3102
	return 0;
3103 3104
}

3105
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3106

3107 3108
int sdhci_resume_host(struct sdhci_host *host)
{
3109
	struct mmc_host *mmc = host->mmc;
3110
	int ret = 0;
3111

3112
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3113 3114 3115
		if (host->ops->enable_dma)
			host->ops->enable_dma(host);
	}
3116

3117 3118 3119 3120 3121 3122
	if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
	    (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
		/* Card keeps power but host controller does not */
		sdhci_init(host, 0);
		host->pwr = 0;
		host->clock = 0;
3123
		mmc->ops->set_ios(mmc, &mmc->ios);
3124 3125 3126 3127
	} else {
		sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
		mmiowb();
	}
3128

3129 3130 3131
	if (host->irq_wake_enabled) {
		sdhci_disable_irq_wakeups(host);
	} else {
3132 3133 3134 3135 3136 3137 3138
		ret = request_threaded_irq(host->irq, sdhci_irq,
					   sdhci_thread_irq, IRQF_SHARED,
					   mmc_hostname(host->mmc), host);
		if (ret)
			return ret;
	}

3139 3140
	sdhci_enable_card_detection(host);

3141
	return ret;
3142 3143
}

3144
EXPORT_SYMBOL_GPL(sdhci_resume_host);
3145 3146 3147 3148 3149

int sdhci_runtime_suspend_host(struct sdhci_host *host)
{
	unsigned long flags;

3150
	mmc_retune_timer_stop(host->mmc);
3151 3152

	spin_lock_irqsave(&host->lock, flags);
3153 3154 3155
	host->ier &= SDHCI_INT_CARD_INT;
	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3156 3157
	spin_unlock_irqrestore(&host->lock, flags);

3158
	synchronize_hardirq(host->irq);
3159 3160 3161 3162 3163

	spin_lock_irqsave(&host->lock, flags);
	host->runtime_suspended = true;
	spin_unlock_irqrestore(&host->lock, flags);

3164
	return 0;
3165 3166 3167 3168 3169
}
EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);

int sdhci_runtime_resume_host(struct sdhci_host *host)
{
3170
	struct mmc_host *mmc = host->mmc;
3171
	unsigned long flags;
3172
	int host_flags = host->flags;
3173 3174 3175 3176 3177 3178 3179 3180

	if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
		if (host->ops->enable_dma)
			host->ops->enable_dma(host);
	}

	sdhci_init(host, 0);

3181 3182
	if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
	    mmc->ios.power_mode != MMC_POWER_OFF) {
3183 3184 3185 3186 3187
		/* Force clock and power re-program */
		host->pwr = 0;
		host->clock = 0;
		mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
		mmc->ops->set_ios(mmc, &mmc->ios);
3188

3189 3190 3191 3192 3193 3194
		if ((host_flags & SDHCI_PV_ENABLED) &&
		    !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
			spin_lock_irqsave(&host->lock, flags);
			sdhci_enable_preset_value(host, true);
			spin_unlock_irqrestore(&host->lock, flags);
		}
3195

3196 3197 3198 3199
		if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
		    mmc->ops->hs400_enhanced_strobe)
			mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
	}
3200

3201 3202 3203 3204 3205
	spin_lock_irqsave(&host->lock, flags);

	host->runtime_suspended = false;

	/* Enable SDIO IRQ */
3206
	if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3207 3208 3209 3210 3211 3212 3213
		sdhci_enable_sdio_irq_nolock(host, true);

	/* Enable Card Detection */
	sdhci_enable_card_detection(host);

	spin_unlock_irqrestore(&host->lock, flags);

3214
	return 0;
3215 3216 3217
}
EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);

3218
#endif /* CONFIG_PM */
3219

3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241
/*****************************************************************************\
 *                                                                           *
 * Command Queue Engine (CQE) helpers                                        *
 *                                                                           *
\*****************************************************************************/

void sdhci_cqe_enable(struct mmc_host *mmc)
{
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;
	u8 ctrl;

	spin_lock_irqsave(&host->lock, flags);

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	if (host->flags & SDHCI_USE_64_BIT_DMA)
		ctrl |= SDHCI_CTRL_ADMA64;
	else
		ctrl |= SDHCI_CTRL_ADMA32;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

3242
	sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332
		     SDHCI_BLOCK_SIZE);

	/* Set maximum timeout */
	sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);

	host->ier = host->cqe_ier;

	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);

	host->cqe_on = true;

	pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
		 mmc_hostname(mmc), host->ier,
		 sdhci_readl(host, SDHCI_INT_STATUS));

	mmiowb();
	spin_unlock_irqrestore(&host->lock, flags);
}
EXPORT_SYMBOL_GPL(sdhci_cqe_enable);

void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
{
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);

	sdhci_set_default_irqs(host);

	host->cqe_on = false;

	if (recovery) {
		sdhci_do_reset(host, SDHCI_RESET_CMD);
		sdhci_do_reset(host, SDHCI_RESET_DATA);
	}

	pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
		 mmc_hostname(mmc), host->ier,
		 sdhci_readl(host, SDHCI_INT_STATUS));

	mmiowb();
	spin_unlock_irqrestore(&host->lock, flags);
}
EXPORT_SYMBOL_GPL(sdhci_cqe_disable);

bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
		   int *data_error)
{
	u32 mask;

	if (!host->cqe_on)
		return false;

	if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
		*cmd_error = -EILSEQ;
	else if (intmask & SDHCI_INT_TIMEOUT)
		*cmd_error = -ETIMEDOUT;
	else
		*cmd_error = 0;

	if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
		*data_error = -EILSEQ;
	else if (intmask & SDHCI_INT_DATA_TIMEOUT)
		*data_error = -ETIMEDOUT;
	else if (intmask & SDHCI_INT_ADMA_ERROR)
		*data_error = -EIO;
	else
		*data_error = 0;

	/* Clear selected interrupts. */
	mask = intmask & host->cqe_ier;
	sdhci_writel(host, mask, SDHCI_INT_STATUS);

	if (intmask & SDHCI_INT_BUS_POWER)
		pr_err("%s: Card is consuming too much power!\n",
		       mmc_hostname(host->mmc));

	intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
	if (intmask) {
		sdhci_writel(host, intmask, SDHCI_INT_STATUS);
		pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
		       mmc_hostname(host->mmc), intmask);
		sdhci_dumpregs(host);
	}

	return true;
}
EXPORT_SYMBOL_GPL(sdhci_cqe_irq);

3333 3334
/*****************************************************************************\
 *                                                                           *
3335
 * Device allocation/registration                                            *
3336 3337 3338
 *                                                                           *
\*****************************************************************************/

3339 3340
struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size)
3341 3342 3343 3344
{
	struct mmc_host *mmc;
	struct sdhci_host *host;

3345
	WARN_ON(dev == NULL);
3346

3347
	mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3348
	if (!mmc)
3349
		return ERR_PTR(-ENOMEM);
3350 3351 3352

	host = mmc_priv(mmc);
	host->mmc = mmc;
3353 3354
	host->mmc_host_ops = sdhci_ops;
	mmc->ops = &host->mmc_host_ops;
3355

3356 3357
	host->flags = SDHCI_SIGNALING_330;

3358 3359 3360
	host->cqe_ier     = SDHCI_CQE_INT_MASK;
	host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;

3361 3362
	host->tuning_delay = -1;

3363 3364
	host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;

3365 3366
	return host;
}
3367

3368
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3369

3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399
static int sdhci_set_dma_mask(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;
	struct device *dev = mmc_dev(mmc);
	int ret = -EINVAL;

	if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
		host->flags &= ~SDHCI_USE_64_BIT_DMA;

	/* Try 64-bit mask if hardware is capable  of it */
	if (host->flags & SDHCI_USE_64_BIT_DMA) {
		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
		if (ret) {
			pr_warn("%s: Failed to set 64-bit DMA mask.\n",
				mmc_hostname(mmc));
			host->flags &= ~SDHCI_USE_64_BIT_DMA;
		}
	}

	/* 32-bit mask as default & fallback */
	if (ret) {
		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
		if (ret)
			pr_warn("%s: Failed to set 32-bit DMA mask.\n",
				mmc_hostname(mmc));
	}

	return ret;
}

3400 3401 3402
void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
{
	u16 v;
3403 3404
	u64 dt_caps_mask = 0;
	u64 dt_caps = 0;
3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418

	if (host->read_caps)
		return;

	host->read_caps = true;

	if (debug_quirks)
		host->quirks = debug_quirks;

	if (debug_quirks2)
		host->quirks2 = debug_quirks2;

	sdhci_do_reset(host, SDHCI_RESET_ALL);

3419 3420 3421 3422 3423
	of_property_read_u64(mmc_dev(host->mmc)->of_node,
			     "sdhci-caps-mask", &dt_caps_mask);
	of_property_read_u64(mmc_dev(host->mmc)->of_node,
			     "sdhci-caps", &dt_caps);

3424 3425 3426 3427 3428 3429
	v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
	host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;

	if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
		return;

3430 3431 3432 3433 3434 3435 3436
	if (caps) {
		host->caps = *caps;
	} else {
		host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
		host->caps &= ~lower_32_bits(dt_caps_mask);
		host->caps |= lower_32_bits(dt_caps);
	}
3437 3438 3439 3440

	if (host->version < SDHCI_SPEC_300)
		return;

3441 3442 3443 3444 3445 3446 3447
	if (caps1) {
		host->caps1 = *caps1;
	} else {
		host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
		host->caps1 &= ~upper_32_bits(dt_caps_mask);
		host->caps1 |= upper_32_bits(dt_caps);
	}
3448 3449 3450
}
EXPORT_SYMBOL_GPL(__sdhci_read_caps);

3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512
static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;
	unsigned int max_blocks;
	unsigned int bounce_size;
	int ret;

	/*
	 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
	 * has diminishing returns, this is probably because SD/MMC
	 * cards are usually optimized to handle this size of requests.
	 */
	bounce_size = SZ_64K;
	/*
	 * Adjust downwards to maximum request size if this is less
	 * than our segment size, else hammer down the maximum
	 * request size to the maximum buffer size.
	 */
	if (mmc->max_req_size < bounce_size)
		bounce_size = mmc->max_req_size;
	max_blocks = bounce_size / 512;

	/*
	 * When we just support one segment, we can get significant
	 * speedups by the help of a bounce buffer to group scattered
	 * reads/writes together.
	 */
	host->bounce_buffer = devm_kmalloc(mmc->parent,
					   bounce_size,
					   GFP_KERNEL);
	if (!host->bounce_buffer) {
		pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
		       mmc_hostname(mmc),
		       bounce_size);
		/*
		 * Exiting with zero here makes sure we proceed with
		 * mmc->max_segs == 1.
		 */
		return 0;
	}

	host->bounce_addr = dma_map_single(mmc->parent,
					   host->bounce_buffer,
					   bounce_size,
					   DMA_BIDIRECTIONAL);
	ret = dma_mapping_error(mmc->parent, host->bounce_addr);
	if (ret)
		/* Again fall back to max_segs == 1 */
		return 0;
	host->bounce_buffer_size = bounce_size;

	/* Lie about this since we're bouncing */
	mmc->max_segs = max_blocks;
	mmc->max_seg_size = bounce_size;
	mmc->max_req_size = bounce_size;

	pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
		mmc_hostname(mmc), max_blocks, bounce_size);

	return 0;
}

3513
int sdhci_setup_host(struct sdhci_host *host)
3514 3515
{
	struct mmc_host *mmc;
3516 3517
	u32 max_current_caps;
	unsigned int ocr_avail;
3518
	unsigned int override_timeout_clk;
3519
	u32 max_clk;
3520
	int ret;
3521

3522 3523 3524
	WARN_ON(host == NULL);
	if (host == NULL)
		return -EINVAL;
3525

3526
	mmc = host->mmc;
3527

3528 3529 3530 3531 3532 3533 3534
	/*
	 * If there are external regulators, get them. Note this must be done
	 * early before resetting the host and reading the capabilities so that
	 * the host can take the appropriate action if regulators are not
	 * available.
	 */
	ret = mmc_regulator_get_supply(mmc);
3535
	if (ret)
3536 3537
		return ret;

3538 3539 3540 3541 3542 3543 3544
	DBG("Version:   0x%08x | Present:  0x%08x\n",
	    sdhci_readw(host, SDHCI_HOST_VERSION),
	    sdhci_readl(host, SDHCI_PRESENT_STATE));
	DBG("Caps:      0x%08x | Caps_1:   0x%08x\n",
	    sdhci_readl(host, SDHCI_CAPABILITIES),
	    sdhci_readl(host, SDHCI_CAPABILITIES_1));

3545
	sdhci_read_caps(host);
3546

3547 3548
	override_timeout_clk = host->timeout_clk;

3549
	if (host->version > SDHCI_SPEC_300) {
3550 3551
		pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
		       mmc_hostname(mmc), host->version);
3552 3553
	}

3554
	if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3555
		host->flags |= SDHCI_USE_SDMA;
3556
	else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3557
		DBG("Controller doesn't have SDMA capability\n");
3558
	else
3559
		host->flags |= SDHCI_USE_SDMA;
3560

3561
	if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3562
		(host->flags & SDHCI_USE_SDMA)) {
3563
		DBG("Disabling DMA as it is marked broken\n");
3564
		host->flags &= ~SDHCI_USE_SDMA;
3565 3566
	}

3567
	if ((host->version >= SDHCI_SPEC_200) &&
3568
		(host->caps & SDHCI_CAN_DO_ADMA2))
3569
		host->flags |= SDHCI_USE_ADMA;
3570 3571 3572 3573 3574 3575 3576

	if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
		(host->flags & SDHCI_USE_ADMA)) {
		DBG("Disabling ADMA as it is marked broken\n");
		host->flags &= ~SDHCI_USE_ADMA;
	}

3577 3578 3579 3580 3581 3582 3583
	/*
	 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
	 * and *must* do 64-bit DMA.  A driver has the opportunity to change
	 * that during the first call to ->enable_dma().  Similarly
	 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
	 * implement.
	 */
3584
	if (host->caps & SDHCI_CAN_64BIT)
3585 3586
		host->flags |= SDHCI_USE_64_BIT_DMA;

3587
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598
		ret = sdhci_set_dma_mask(host);

		if (!ret && host->ops->enable_dma)
			ret = host->ops->enable_dma(host);

		if (ret) {
			pr_warn("%s: No suitable DMA available - falling back to PIO\n",
				mmc_hostname(mmc));
			host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);

			ret = 0;
3599 3600 3601
		}
	}

3602 3603 3604 3605
	/* SDMA does not support 64-bit DMA */
	if (host->flags & SDHCI_USE_64_BIT_DMA)
		host->flags &= ~SDHCI_USE_SDMA;

3606
	if (host->flags & SDHCI_USE_ADMA) {
3607 3608 3609
		dma_addr_t dma;
		void *buf;

3610
		/*
3611 3612 3613 3614
		 * The DMA descriptor table size is calculated as the maximum
		 * number of segments times 2, to allow for an alignment
		 * descriptor for each segment, plus 1 for a nop end descriptor,
		 * all multipled by the descriptor size.
3615
		 */
3616 3617 3618 3619 3620 3621 3622 3623 3624
		if (host->flags & SDHCI_USE_64_BIT_DMA) {
			host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
					      SDHCI_ADMA2_64_DESC_SZ;
			host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
		} else {
			host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
					      SDHCI_ADMA2_32_DESC_SZ;
			host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
		}
3625

3626
		host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3627 3628 3629
		buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
					 host->adma_table_sz, &dma, GFP_KERNEL);
		if (!buf) {
3630
			pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3631 3632
				mmc_hostname(mmc));
			host->flags &= ~SDHCI_USE_ADMA;
3633 3634
		} else if ((dma + host->align_buffer_sz) &
			   (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3635 3636
			pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
				mmc_hostname(mmc));
3637
			host->flags &= ~SDHCI_USE_ADMA;
3638 3639 3640 3641 3642
			dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
					  host->adma_table_sz, buf, dma);
		} else {
			host->align_buffer = buf;
			host->align_addr = dma;
3643

3644 3645 3646
			host->adma_table = buf + host->align_buffer_sz;
			host->adma_addr = dma + host->align_buffer_sz;
		}
3647 3648
	}

3649 3650 3651 3652 3653
	/*
	 * If we use DMA, then it's up to the caller to set the DMA
	 * mask, but PIO does not need the hw shim so we set a new
	 * mask here in that case.
	 */
3654
	if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3655
		host->dma_mask = DMA_BIT_MASK(64);
3656
		mmc_dev(mmc)->dma_mask = &host->dma_mask;
3657
	}
3658

3659
	if (host->version >= SDHCI_SPEC_300)
3660
		host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3661 3662
			>> SDHCI_CLOCK_BASE_SHIFT;
	else
3663
		host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3664 3665
			>> SDHCI_CLOCK_BASE_SHIFT;

3666
	host->max_clk *= 1000000;
3667 3668
	if (host->max_clk == 0 || host->quirks &
			SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3669
		if (!host->ops->get_max_clock) {
3670 3671
			pr_err("%s: Hardware doesn't specify base clock frequency.\n",
			       mmc_hostname(mmc));
3672 3673
			ret = -ENODEV;
			goto undma;
3674 3675
		}
		host->max_clk = host->ops->get_max_clock(host);
3676
	}
3677

3678 3679 3680 3681
	/*
	 * In case of Host Controller v3.00, find out whether clock
	 * multiplier is supported.
	 */
3682
	host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693
			SDHCI_CLOCK_MUL_SHIFT;

	/*
	 * In case the value in Clock Multiplier is 0, then programmable
	 * clock mode is not supported, otherwise the actual clock
	 * multiplier is one more than the value of Clock Multiplier
	 * in the Capabilities Register.
	 */
	if (host->clk_mul)
		host->clk_mul += 1;

3694 3695 3696
	/*
	 * Set host parameters.
	 */
3697 3698
	max_clk = host->max_clk;

3699
	if (host->ops->get_min_clock)
3700
		mmc->f_min = host->ops->get_min_clock(host);
3701 3702 3703
	else if (host->version >= SDHCI_SPEC_300) {
		if (host->clk_mul) {
			mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3704
			max_clk = host->max_clk * host->clk_mul;
3705 3706 3707
		} else
			mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
	} else
3708
		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3709

3710
	if (!mmc->f_max || mmc->f_max > max_clk)
3711 3712
		mmc->f_max = max_clk;

3713
	if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3714
		host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3715
					SDHCI_TIMEOUT_CLK_SHIFT;
3716 3717 3718 3719

		if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
			host->timeout_clk *= 1000;

3720
		if (host->timeout_clk == 0) {
3721
			if (!host->ops->get_timeout_clock) {
3722 3723
				pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
					mmc_hostname(mmc));
3724 3725
				ret = -ENODEV;
				goto undma;
3726
			}
3727

3728 3729 3730 3731
			host->timeout_clk =
				DIV_ROUND_UP(host->ops->get_timeout_clock(host),
					     1000);
		}
3732

3733 3734 3735
		if (override_timeout_clk)
			host->timeout_clk = override_timeout_clk;

3736
		mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3737
			host->ops->get_max_timeout_count(host) : 1 << 27;
3738 3739
		mmc->max_busy_timeout /= host->timeout_clk;
	}
3740

3741 3742 3743 3744
	if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
	    !host->ops->get_max_timeout_count)
		mmc->max_busy_timeout = 0;

3745
	mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3746
	mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3747 3748 3749

	if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
		host->flags |= SDHCI_AUTO_CMD12;
3750

3751
	/* Auto-CMD23 stuff only works in ADMA or PIO. */
3752
	if ((host->version >= SDHCI_SPEC_300) &&
3753
	    ((host->flags & SDHCI_USE_ADMA) ||
3754 3755
	     !(host->flags & SDHCI_USE_SDMA)) &&
	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3756
		host->flags |= SDHCI_AUTO_CMD23;
3757
		DBG("Auto-CMD23 available\n");
3758
	} else {
3759
		DBG("Auto-CMD23 unavailable\n");
3760 3761
	}

3762 3763 3764 3765 3766 3767 3768
	/*
	 * A controller may support 8-bit width, but the board itself
	 * might not have the pins brought out.  Boards that support
	 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
	 * their platform code before calling sdhci_add_host(), and we
	 * won't assume 8-bit width for hosts without that CAP.
	 */
3769
	if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3770
		mmc->caps |= MMC_CAP_4_BIT_DATA;
3771

3772 3773 3774
	if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
		mmc->caps &= ~MMC_CAP_CMD23;

3775
	if (host->caps & SDHCI_CAN_DO_HISPD)
3776
		mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3777

3778
	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3779
	    mmc_card_is_removable(mmc) &&
3780
	    mmc_gpio_get_cd(host->mmc) < 0)
3781 3782
		mmc->caps |= MMC_CAP_NEEDS_POLL;

3783 3784
	if (!IS_ERR(mmc->supply.vqmmc)) {
		ret = regulator_enable(mmc->supply.vqmmc);
3785 3786

		/* If vqmmc provides no 1.8V signalling, then there's no UHS */
3787 3788
		if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
						    1950000))
3789 3790 3791
			host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
					 SDHCI_SUPPORT_SDR50 |
					 SDHCI_SUPPORT_DDR50);
3792 3793 3794 3795 3796 3797

		/* In eMMC case vqmmc might be a fixed 1.8V regulator */
		if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
						    3600000))
			host->flags &= ~SDHCI_SIGNALING_330;

3798 3799 3800
		if (ret) {
			pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
				mmc_hostname(mmc), ret);
3801
			mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3802
		}
3803
	}
3804

3805 3806 3807
	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
		host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
				 SDHCI_SUPPORT_DDR50);
3808 3809 3810 3811 3812 3813 3814 3815 3816 3817
		/*
		 * The SDHCI controller in a SoC might support HS200/HS400
		 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
		 * but if the board is modeled such that the IO lines are not
		 * connected to 1.8v then HS200/HS400 cannot be supported.
		 * Disable HS200/HS400 if the board does not have 1.8v connected
		 * to the IO lines. (Applicable for other modes in 1.8v)
		 */
		mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
		mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
3818
	}
3819

3820
	/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3821 3822
	if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
			   SDHCI_SUPPORT_DDR50))
3823 3824 3825
		mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;

	/* SDR104 supports also implies SDR50 support */
3826
	if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3827
		mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3828 3829 3830
		/* SD3.0: SDR104 is supported so (for eMMC) the caps2
		 * field can be promoted to support HS200.
		 */
3831
		if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3832
			mmc->caps2 |= MMC_CAP2_HS200;
3833
	} else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3834
		mmc->caps |= MMC_CAP_UHS_SDR50;
3835
	}
3836

3837
	if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3838
	    (host->caps1 & SDHCI_SUPPORT_HS400))
3839 3840
		mmc->caps2 |= MMC_CAP2_HS400;

3841 3842 3843 3844 3845 3846
	if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
	    (IS_ERR(mmc->supply.vqmmc) ||
	     !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
					     1300000)))
		mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;

3847 3848
	if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
	    !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3849 3850
		mmc->caps |= MMC_CAP_UHS_DDR50;

3851
	/* Does the host need tuning for SDR50? */
3852
	if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3853 3854
		host->flags |= SDHCI_SDR50_NEEDS_TUNING;

3855
	/* Driver Type(s) (A, C, D) supported by the host */
3856
	if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3857
		mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3858
	if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3859
		mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3860
	if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3861 3862
		mmc->caps |= MMC_CAP_DRIVER_TYPE_D;

3863
	/* Initial value for re-tuning timer count */
3864 3865
	host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
			     SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3866 3867 3868 3869 3870 3871 3872 3873 3874

	/*
	 * In case Re-tuning Timer is not disabled, the actual value of
	 * re-tuning timer will be 2 ^ (n - 1).
	 */
	if (host->tuning_count)
		host->tuning_count = 1 << (host->tuning_count - 1);

	/* Re-tuning mode supported by the Host Controller */
3875
	host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3876 3877
			     SDHCI_RETUNING_MODE_SHIFT;

3878
	ocr_avail = 0;
3879

3880 3881 3882 3883 3884 3885 3886 3887
	/*
	 * According to SD Host Controller spec v3.00, if the Host System
	 * can afford more than 150mA, Host Driver should set XPC to 1. Also
	 * the value is meaningful only if Voltage Support in the Capabilities
	 * register is set. The actual current value is 4 times the register
	 * value.
	 */
	max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3888
	if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3889
		int curr = regulator_get_current_limit(mmc->supply.vmmc);
3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902
		if (curr > 0) {

			/* convert to SDHCI_MAX_CURRENT format */
			curr = curr/1000;  /* convert to mA */
			curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;

			curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
			max_current_caps =
				(curr << SDHCI_MAX_CURRENT_330_SHIFT) |
				(curr << SDHCI_MAX_CURRENT_300_SHIFT) |
				(curr << SDHCI_MAX_CURRENT_180_SHIFT);
		}
	}
3903

3904
	if (host->caps & SDHCI_CAN_VDD_330) {
3905
		ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3906

3907
		mmc->max_current_330 = ((max_current_caps &
3908 3909 3910 3911
				   SDHCI_MAX_CURRENT_330_MASK) >>
				   SDHCI_MAX_CURRENT_330_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}
3912
	if (host->caps & SDHCI_CAN_VDD_300) {
3913
		ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3914

3915
		mmc->max_current_300 = ((max_current_caps &
3916 3917 3918 3919
				   SDHCI_MAX_CURRENT_300_MASK) >>
				   SDHCI_MAX_CURRENT_300_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}
3920
	if (host->caps & SDHCI_CAN_VDD_180) {
3921 3922
		ocr_avail |= MMC_VDD_165_195;

3923
		mmc->max_current_180 = ((max_current_caps &
3924 3925 3926 3927 3928
				   SDHCI_MAX_CURRENT_180_MASK) >>
				   SDHCI_MAX_CURRENT_180_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}

3929 3930 3931 3932 3933
	/* If OCR set by host, use it instead. */
	if (host->ocr_mask)
		ocr_avail = host->ocr_mask;

	/* If OCR set by external regulators, give it highest prio. */
3934
	if (mmc->ocr_avail)
3935
		ocr_avail = mmc->ocr_avail;
3936

3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948
	mmc->ocr_avail = ocr_avail;
	mmc->ocr_avail_sdio = ocr_avail;
	if (host->ocr_avail_sdio)
		mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
	mmc->ocr_avail_sd = ocr_avail;
	if (host->ocr_avail_sd)
		mmc->ocr_avail_sd &= host->ocr_avail_sd;
	else /* normal SD controllers don't support 1.8V */
		mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
	mmc->ocr_avail_mmc = ocr_avail;
	if (host->ocr_avail_mmc)
		mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3949 3950

	if (mmc->ocr_avail == 0) {
3951 3952
		pr_err("%s: Hardware doesn't report any support voltages.\n",
		       mmc_hostname(mmc));
3953 3954
		ret = -ENODEV;
		goto unreg;
3955 3956
	}

3957 3958 3959 3960 3961 3962 3963 3964 3965
	if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
			  MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
			  MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
	    (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
		host->flags |= SDHCI_SIGNALING_180;

	if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
		host->flags |= SDHCI_SIGNALING_120;

3966 3967
	spin_lock_init(&host->lock);

3968 3969 3970 3971 3972 3973 3974
	/*
	 * Maximum number of sectors in one transfer. Limited by SDMA boundary
	 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
	 * is less anyway.
	 */
	mmc->max_req_size = 524288;

3975
	/*
3976 3977
	 * Maximum number of segments. Depends on if the hardware
	 * can do scatter/gather or not.
3978
	 */
3979
	if (host->flags & SDHCI_USE_ADMA) {
3980
		mmc->max_segs = SDHCI_MAX_SEGS;
3981
	} else if (host->flags & SDHCI_USE_SDMA) {
3982
		mmc->max_segs = 1;
3983 3984 3985 3986 3987 3988 3989
		if (swiotlb_max_segment()) {
			unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
						IO_TLB_SEGSIZE;
			mmc->max_req_size = min(mmc->max_req_size,
						max_req_size);
		}
	} else { /* PIO */
3990
		mmc->max_segs = SDHCI_MAX_SEGS;
3991
	}
3992 3993 3994

	/*
	 * Maximum segment size. Could be one segment with the maximum number
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	 * of bytes. When doing hardware scatter/gather, each entry cannot
	 * be larger than 64 KiB though.
3997
	 */
3998 3999 4000 4001 4002 4003
	if (host->flags & SDHCI_USE_ADMA) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
			mmc->max_seg_size = 65535;
		else
			mmc->max_seg_size = 65536;
	} else {
4004
		mmc->max_seg_size = mmc->max_req_size;
4005
	}
4006

4007 4008 4009 4010
	/*
	 * Maximum block size. This varies from controller to controller and
	 * is specified in the capabilities register.
	 */
4011 4012 4013
	if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
		mmc->max_blk_size = 2;
	} else {
4014
		mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4015 4016
				SDHCI_MAX_BLOCK_SHIFT;
		if (mmc->max_blk_size >= 3) {
4017 4018
			pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
				mmc_hostname(mmc));
4019 4020 4021 4022 4023
			mmc->max_blk_size = 0;
		}
	}

	mmc->max_blk_size = 512 << mmc->max_blk_size;
4024

4025 4026 4027
	/*
	 * Maximum block count.
	 */
4028
	mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4029

4030 4031 4032 4033 4034 4035 4036
	if (mmc->max_segs == 1) {
		/* This may alter mmc->*_blk_* parameters */
		ret = sdhci_allocate_bounce_buffer(host);
		if (ret)
			return ret;
	}

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	return 0;

unreg:
	if (!IS_ERR(mmc->supply.vqmmc))
		regulator_disable(mmc->supply.vqmmc);
undma:
	if (host->align_buffer)
		dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
				  host->adma_table_sz, host->align_buffer,
				  host->align_addr);
	host->adma_table = NULL;
	host->align_buffer = NULL;

	return ret;
}
EXPORT_SYMBOL_GPL(sdhci_setup_host);

4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069
void sdhci_cleanup_host(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;

	if (!IS_ERR(mmc->supply.vqmmc))
		regulator_disable(mmc->supply.vqmmc);

	if (host->align_buffer)
		dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
				  host->adma_table_sz, host->align_buffer,
				  host->align_addr);
	host->adma_table = NULL;
	host->align_buffer = NULL;
}
EXPORT_SYMBOL_GPL(sdhci_cleanup_host);

4070 4071 4072 4073 4074
int __sdhci_add_host(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;
	int ret;

4075 4076 4077 4078 4079 4080
	/*
	 * Init tasklets.
	 */
	tasklet_init(&host->finish_tasklet,
		sdhci_tasklet_finish, (unsigned long)host);

4081 4082
	timer_setup(&host->timer, sdhci_timeout_timer, 0);
	timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4083

4084
	init_waitqueue_head(&host->buf_ready_int);
4085

4086 4087
	sdhci_init(host, 0);

4088 4089
	ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
				   IRQF_SHARED,	mmc_hostname(mmc), host);
4090 4091 4092
	if (ret) {
		pr_err("%s: Failed to request IRQ %d: %d\n",
		       mmc_hostname(mmc), host->irq, ret);
4093
		goto untasklet;
4094
	}
4095

4096
	ret = sdhci_led_register(host);
4097 4098 4099
	if (ret) {
		pr_err("%s: Failed to register LED device: %d\n",
		       mmc_hostname(mmc), ret);
4100
		goto unirq;
4101
	}
4102

4103 4104
	mmiowb();

4105 4106 4107
	ret = mmc_add_host(mmc);
	if (ret)
		goto unled;
4108

4109
	pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4110
		mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4111 4112
		(host->flags & SDHCI_USE_ADMA) ?
		(host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4113
		(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4114

4115 4116
	sdhci_enable_card_detection(host);

4117 4118
	return 0;

4119
unled:
4120
	sdhci_led_unregister(host);
4121
unirq:
4122
	sdhci_do_reset(host, SDHCI_RESET_ALL);
4123 4124
	sdhci_writel(host, 0, SDHCI_INT_ENABLE);
	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4125
	free_irq(host->irq, host);
4126
untasklet:
4127
	tasklet_kill(&host->finish_tasklet);
4128

4129 4130
	return ret;
}
4131 4132 4133 4134 4135 4136 4137 4138 4139
EXPORT_SYMBOL_GPL(__sdhci_add_host);

int sdhci_add_host(struct sdhci_host *host)
{
	int ret;

	ret = sdhci_setup_host(host);
	if (ret)
		return ret;
4140

4141 4142 4143 4144 4145 4146 4147 4148 4149 4150
	ret = __sdhci_add_host(host);
	if (ret)
		goto cleanup;

	return 0;

cleanup:
	sdhci_cleanup_host(host);

	return ret;
4151
}
4152
EXPORT_SYMBOL_GPL(sdhci_add_host);
4153

Pierre Ossman's avatar
Pierre Ossman committed
4154
void sdhci_remove_host(struct sdhci_host *host, int dead)
4155
{
4156
	struct mmc_host *mmc = host->mmc;
Pierre Ossman's avatar
Pierre Ossman committed
4157 4158 4159 4160 4161 4162 4163
	unsigned long flags;

	if (dead) {
		spin_lock_irqsave(&host->lock, flags);

		host->flags |= SDHCI_DEVICE_DEAD;

4164
		if (sdhci_has_requests(host)) {
4165
			pr_err("%s: Controller removed during "
4166
				" transfer!\n", mmc_hostname(mmc));
4167
			sdhci_error_out_mrqs(host, -ENOMEDIUM);
Pierre Ossman's avatar
Pierre Ossman committed
4168 4169 4170 4171 4172
		}

		spin_unlock_irqrestore(&host->lock, flags);
	}

4173 4174
	sdhci_disable_card_detection(host);

4175
	mmc_remove_host(mmc);
4176

4177
	sdhci_led_unregister(host);
4178

Pierre Ossman's avatar
Pierre Ossman committed
4179
	if (!dead)
4180
		sdhci_do_reset(host, SDHCI_RESET_ALL);
4181

4182 4183
	sdhci_writel(host, 0, SDHCI_INT_ENABLE);
	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4184 4185 4186
	free_irq(host->irq, host);

	del_timer_sync(&host->timer);
4187
	del_timer_sync(&host->data_timer);
4188 4189

	tasklet_kill(&host->finish_tasklet);
4190

4191 4192
	if (!IS_ERR(mmc->supply.vqmmc))
		regulator_disable(mmc->supply.vqmmc);
4193

4194
	if (host->align_buffer)
4195 4196 4197
		dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
				  host->adma_table_sz, host->align_buffer,
				  host->align_addr);
4198

4199
	host->adma_table = NULL;
4200
	host->align_buffer = NULL;
4201 4202
}

4203
EXPORT_SYMBOL_GPL(sdhci_remove_host);
4204

4205
void sdhci_free_host(struct sdhci_host *host)
4206
{
4207
	mmc_free_host(host->mmc);
4208 4209
}

4210
EXPORT_SYMBOL_GPL(sdhci_free_host);
4211 4212 4213 4214 4215 4216 4217 4218 4219

/*****************************************************************************\
 *                                                                           *
 * Driver init/exit                                                          *
 *                                                                           *
\*****************************************************************************/

static int __init sdhci_drv_init(void)
{
4220
	pr_info(DRIVER_NAME
4221
		": Secure Digital Host Controller Interface driver\n");
4222
	pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4223

4224
	return 0;
4225 4226 4227 4228 4229 4230 4231 4232 4233
}

static void __exit sdhci_drv_exit(void)
{
}

module_init(sdhci_drv_init);
module_exit(sdhci_drv_exit);

4234
module_param(debug_quirks, uint, 0444);
4235
module_param(debug_quirks2, uint, 0444);
4236

4237
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4238
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4239
MODULE_LICENSE("GPL");
4240

4241
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4242
MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");