- 16 Dec, 2023 27 commits
-
-
Bartosz Golaszewski authored
Add the Bluetooth node for RB5 as well as its dependencies in the form of the uart6 -> serial1 alias and the pin function for the Bluetooth enable GPIO. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231207090706.19134-1-brgl@bgdev.plSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
-
Manivannan Sadhasivam authored
Add missing space between node name and braces to match the style. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-4-manivannan.sadhasivam@linaro.orgSigned-off-by:
-
Manivannan Sadhasivam authored
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by:
-
Nikita Travkin authored
This laptop has two i2s speakers; an i2s audio codec for the headset jack; two DMIC microphones in the lid and the displayport audio channel. This commit adds the audio node that describes all of the above with the exception of the DMICs that require in-SoC digital codec to be brought up, which will be done later. Note that the displayport channel is connected here for completeness, but the displayport can't be used yet since the HPD signal is created by the embedded controller, which will be added later. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Nikita Travkin <nikita@trvn.ru> Link: https://lore.kernel.org/r/20231205-aspire1-sound-v2-3-443b7ac0a06f@trvn.ruSigned-off-by:
-
Nikita Travkin authored
When initially added, a mistake was made in the definition of the codec. Despite the fact that the DMIC line is connected on the side of the codec chip, and relevant passive components, including 0-ohm resistors connecting the dmics, are present, the dmic line is still cut in another place on the board, which was overlooked. Correct this by replacing the dmic configuration with a comment describing this hardware detail. While at it, also add missing regulators definitions. This is not a functional change as all the relevant regulators were already added via the other rail supplies. Fixes: 4a9f8f8f ("arm64: dts: qcom: Add Acer Aspire 1") Signed-off-by:
-
Nikita Travkin authored
pm6150 has a read-only RTC that can be used to keep the time with some extra userspace tools. Enable it. Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-10-dmitry.baryshkov@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Dmitry Baryshkov authored
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by:
-
Konrad Dybcio authored
Enable the GPU and provide a path for the ZAP blob. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
-
Konrad Dybcio authored
Enable the GPU and provide a path for the ZAP blob. Reviewed-by:
-
Konrad Dybcio authored
Enable the GPU and provide a path for the ZAP blob. Reviewed-by:
-
Konrad Dybcio authored
Add the required nodes to support the A740 GPU. Signed-off-by:
-
Konrad Dybcio authored
Add the required nodes to support the A730 GPU. Reviewed-by:
-
Stephan Gerhold authored
The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this seems to fix some weird issues with UART where both input/output becomes garbled with certain obscure firmware versions on some devices. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.9.1-02310-8x16.0/arch/arm/boot/dts/qcom/msm8939-common.dtsi#L866-872 Cc: stable@vger.kernel.org # 6.5 Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8916-blsp-dma-remote-v1-2-3e49c8838c8d@gerhold.netSigned-off-by:
-
Stephan Gerhold authored
The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this seems to fix some weird issues with UART where both input/output becomes garbled with certain obscure firmware versions on some devices. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.9.1-02310-8x16.0/arch/arm/boot/dts/qcom/msm8916.dtsi#L1466-1472 Cc: stable@vger.kernel.org # 6.5 Fixes: a0e5fb10 ("arm64: dts: qcom: Add msm8916 BLSP device nodes") Signed-off-by:
-
Stephan Gerhold authored
Looks like not all firmware versions used for MSM8939 program the timer frequency for both broadcast/MMIO timers, causing a WARNING at runtime: WARNING: CPU: 0 PID: 0 at kernel/time/clockevents.c:38 cev_delta2ns+0x74/0x90 pc : cev_delta2ns+0x74/0x90 lr : clockevents_config.part.0+0x64/0x8c Call trace: cev_delta2ns+0x74/0x90 clockevents_config_and_register+0x20/0x34 arch_timer_mem_of_init+0x374/0x534 timer_probe+0x88/0x110 time_init+0x14/0x4c start_kernel+0x2c0/0x640 Unfortunately there is no way to fix the firmware on most of these devices since it's proprietary and signed. As a workaround, specify the clock-frequency explicitly in the DT to fix the warning. Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Reported-by:
Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by:
-
Stephan Gerhold authored
Add the missing vio-supply to all usages of the AW2013 LED controller to ensure that the regulator needed for pull-up of the interrupt and I2C lines is really turned on. While this seems to have worked fine so far some of these regulators are not guaranteed to be always-on. For example, pm8916_l6 is typically turned off together with the display if there aren't any other devices (e.g. sensors) keeping it always-on. Cc: stable@vger.kernel.org # 6.6 Signed-off-by:
-
Chukun Pan authored
Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by:
Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203154003.532765-1-amadeus@jmu.edu.cnSigned-off-by:
-
Chukun Pan authored
Add node to support all the QUP UART node controller inside of IPQ6018. Some routers use these bus to connect Bluetooth chips. Signed-off-by:
-
Konrad Dybcio authored
Enable the remote processors and tighten up the regulators to enable Wi-Fi functionality on the RB2. For reference, the hw/sw identifies as: qmi chip_id 0x150 chip_family 0x4002 board_id 0xff soc_id 0x40670000 qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by:
-
- 09 Dec, 2023 9 commits
-
-
Luca Weiss authored
Now that the WPSS remoteproc is enabled, enable wifi so we can use it. Reviewed-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-11-6aa394d33edf@fairphone.comSigned-off-by:
-
Luca Weiss authored
Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Reviewed-by:
-
Luca Weiss authored
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Remove the reserved-memory node from sc7280-chrome-common since CDSP is currently not used there. Acked-by:
-
Luca Weiss authored
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Acked-by:
-
Luca Weiss authored
The wpss-pil driver wants to manage too many resources that cannot be touched with standard Qualcomm firmware. Use the compatible from the PAS driver and move the ChromeOS-specific bits to sc7280-chrome-common.dtsi. Signed-off-by:
-
Luca Weiss authored
Enable the UFS phy and controller so that we can access the internal storage of the phone. At the same time we need to bump the minimum voltage used for UFS VCC, otherwise it doesn't initialize properly. The 2.952V is taken from the vcc-voltage-level property downstream. See also the following link for more information about the VCCQ/VCCQ2: https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/1590a3739e7dc29d2597307881553236d492f188/fp5/yupik-idp-pm7250b.dtsi#207Signed-off-by:
-
Luca Weiss authored
The dtbs_check really doesn't like having memory without reg set. The base address depends on the amount of RAM you have: <= 2.00 GiB RAM: 0x80000000 = 3.00 GiB RAM: 0x40000000 = 3.75 GiB RAM: 0x10000000 (more does not fit into the 32-bit physical address space) So, let's pick one of the values, 0x10000000 which is used on devices with 3.75 GiB RAM. Since the bootloader will update it to what's present on the device it doesn't matter too much. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-msm8953-misc-fixes-v2-1-df86655841d9@z3ntu.xyzSigned-off-by:
-
Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 IDP board. Signed-off-by:
Nitin Rawat <quic_nitirawa@quicinc.com> Acked-by:
-
Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by:
-
- 08 Dec, 2023 4 commits
-
-
Neil Armstrong authored
Declare the displayport controller present on the Qualcomm SM8650 SoC and connected to the USB3/DP Combo PHY. Signed-off-by:
-
Krzysztof Kozlowski authored
The address/size cells in PWM node are needed only if individual LEDs are listed. If multi-led is used, then this leads to dtc W=1 warnings: pm8550.dtsi:65.19-73.5: Warning (avoid_unnecessary_addr_size): /soc@0/spmi@c400000/pmic@1/pwm: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: -
Abel Vesa authored
Add basic support for X1E80100 CRD board dts, which allows it to boot to a shell. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
-
Rajendra Nayak authored
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU and LLCC nodes. Co-developed-by:
-
