Add Toradex Verdin AM62 Yavia.

Link: https://www.toradex.com/products/carrier-board/yaviaSigned-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230615095058.33890-6-francesco@dolcini.itSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add Toradex Verdin AM62 Dahlia.

Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kitSigned-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230615095058.33890-5-francesco@dolcini.itSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

This patch adds the device tree to support Toradex Verdin AM62 a
computer on module which can be used on different carrier boards
and the Toradex Verdin Development Board carrier board.

The module consists of an TI AM62 family SoC (either AM623 or AM625), a
TPS65219 PMIC, a Gigabit Ethernet PHY, 512MB to 2GB of LPDDR4 RAM, an
eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, and optional Parallel
RGB to MIPI DSI bridge plus an optional Bluetooth/Wi-Fi module.

Anything that is not self-contained on the module is disabled by
default.

So far there is no display nor USB role switch supported, apart of that
all the other functionalities are fine.

Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kitSigned-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230615095058.33890-4-francesco@dolcini.itSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add toradex,verdin-am62 for Toradex Verdin AM62 SoM, its
nonwifi and wifi variants and the carrier boards (Dahlia,
Verdin Development Board and Yavia) they may be mated in.

Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230615095058.33890-2-francesco@dolcini.itSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC.
It can be used in combination with different carrier boards.
This module can come with different sizes and models for
DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.

A development Kit, called phyBOARD-Lyra [2] is used as a carrier board
reference design around the AM62x SoM.

Supported features:
  * Debug UART
  * SPI NOR Flash
  * eMMC
  * 2x Ethernet
  * Micro SD card
  * I2C EEPROM
  * I2C RTC
  * GPIO Expander
  * LEDs
  * USB

For more details, see:

[1] Product page SoM: https://www.phytec.com/product/phycore-am62x
[2] Product page CB: https://www.phytec.com/product/phyboard-am62xSigned-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230504140143.1425951-2-w.egorov@phytec.deSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add devicetree bindings for AM62x based phyCORE-AM62 SoM
and phyBOARD-Lyra RDK.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230504140143.1425951-1-w.egorov@phytec.deSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

unit-address should not use a 0x prefix.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230424173623.477577-2-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335.79942-2-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add address entry mapping ESM on J7200.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230504080526.133149-4-n-francis@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add address entry mapping ESM on J721E.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Document the binding for TI K3 ESM (Error Signaling Module) block.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define the wakeup uart pin-mux for completeness and add explicit
muxing for mcu_uart0. This allows the device tree usage in bootloader
and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-6-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c. While at it, describe the board detection eeprom
present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-5-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define the wakeup uart pin-mux for completeness and add explicit
muxing for mcu_uart0. This allows the device tree usage in bootloader
and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-4-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add pinmux required to bring out the i2c and gpios on 40-pin RPi
expansion header on the AM68 SK board.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-3-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable
regions, accordingly split the existing wkup_pmx region as follows to avoid
the non-addressable regions and include the rest of valid WKUP_PADCONFIG
registers. Also update references to old nodes with new ones.

wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24)
wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97)
wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100)

Fixes: b8545f9d ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: <stable@vger.kernel.org> # 6.3
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Thejasvi Konduru <t-konduru@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Aiases are defined at board level, so dropping from soc level
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-7-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define aliases at board level
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add main, mcu, wakeup domain  uart0 pin mux into common board file and it's
reference to uart node.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

main_i2c0 pin mux was duplicated in som and common file.
So removing duplicated node from common file.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview".

For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For the even numbered timers, the CASCADE_EN bit does not do
anything. The timer cascade input routing options are shown in TRM
"Figure 12-3224. Timers Overview". For handling beyond multiplexing, the
driver support for timer cascading should be likely be handled via the
clock framework.

The MCU timer controls are also marked as reserved for
usage by the MCU firmware.

Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-3-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.

The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-2-u-kumar1@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Drop the SoC level aliases as these need to be done at board level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-10-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define the aliases at the board level instead of using generic aliases
at SoC level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-9-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define the aliases at the board level instead of using generic aliases
at SoC level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-8-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Define the wakeup uart pin-mux for completeness. This allows the
device tree usage in bootloader and firmwares that can configure the
same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Explicitly define the pinmux rather than depend on bootloader configured
pinmux for the platform.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-5-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add product links to get reference to schematics and design files
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-3-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Rather than depend on the default pinmuxes, explicitly describe the
pinmux
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-2-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Using a phandle makes it clear which UART we are choosing without needing
to resolve through an alias first.

Especially useful for boards like the TI J721s2-EVM where the alias is
"serial2" but it actually resolves to the 8th UART instance(main_uart8).
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
the case for our attached on-board USB-to-UART converter used for
early kernel console. For all other unconnected/disabled ports this
can be configured in userspace later, DT is not the place for device
configuration, especially when there are already standard ways to
set serial baud in userspace.

Remove setting baud for all disabled serial ports and move setting
it for the couple enabled ports down into the board files.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add pinmux required to bring out the i2c and gpios on 40 pin RPi
expansion header on AM69 SK board.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-9-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-8-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Add wakeup and MCU uart. This allows the device tree usage in
bootloader and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-7-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Enable networking for NFS and basic networking functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-6-nm@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>